Performance Comparison of Noise-Tolerant, High- Performance CMOS Domino Logic Configurations

Year : 2025 | Volume : 12 | Issue : 02 | Page : 35 50
    By

    Hardik Patel,

  • Mitesh Limachia,

  • Purvang Dalal,

  • Sohilkumar Dabhi,

  • Harshit Patel,

  • Mitul Shah,

  1. Assistant Professor, Professor, Faculty of Technology, Dharmsinh Desai University, Nadiad, Gujarat, India
  2. Assistant Professor, Professor, Faculty of Technology, Dharmsinh Desai University, Nadiad, Gujarat, India
  3. Professor, Faculty of Technology, Dharmsinh Desai University, Nadiad, Gujarat, India
  4. Assistant Professor, Faculty of Technology, Dharmsinh Desai University, Nadiad, Gujarat, India
  5. Assistant Professor, Faculty of Technology, Dharmsinh Desai University, Nadiad, Gujarat, India
  6. Assistant Professor, Faculty of Technology, Dharmsinh Desai University, Nadiad, Gujarat, India

Abstract

In high-performance VLSI chip design, domino logic configuration is often preferred over static logic due to its faster operation and smaller area footprint, especially in deep submicron (DSM) technology. However, DSM noise has become a significant challenge in domino-based circuits, leading to compromises in the reliability and signal integrity of integrated circuits (ICs). The switching threshold of domino logic, defined as the input voltage level at which the gate output changes state, is typically determined by the NMOS transistor threshold voltage (Vt). Consequently, domino logic exhibits poor noise tolerance, making it a critical vulnerability in high-performance VLSI design. Additionally, high dynamic power dissipation remains a major drawback of domino circuits. Despite these limitations, wide fan-in domino logic remains widely used in applications such as microprocessors, digital signal processors (DSPs), and dynamic memory systems. However, as the fan-in increases, the delay performance of the circuit tends to degrade significantly. Over the past two decades, several domino- based design techniques have been proposed to address these weaknesses. While these approaches have successfully improved noise tolerance, they often come at the expense of other critical design metrics such as power consumption, delay, or silicon area. As a result, there is a growing demand for noise- tolerant domino techniques that introduce minimal overhead in key design parameters, particularly in today’s DSM technology. In this study, two novel techniques are presented: 1) One technique enhances noise immunity and optimizes the noise immunity vs. power and delay trade-off for wide fan-in circuit configurations. 2) The other technique improves noise tolerance while achieving better delay performance in wide fan-in domino logic. Key findings include: Wide Fan-in (AND8): The Novel technique excels in both ANTE/Power and ANTE/Delay metrics; Small Fan-in (AND2): Bobba’s technique demonstrates significant superiority in ANTE/Power; and ANTE/Delay metrics and Width Adjustment (WMN): Increasing transistor width enhances ANTE, but at the cost of higher power consumption and increased delay in the Novel technique. This research offers a balanced approach to overcoming the challenges associated with domino logic in high-performance VLSI circuits.

Keywords: CMOS, SSRS, RSMRD, Domino logic, PDN, RSDLS, DSM, BSIM4

[This article belongs to Journal of Semiconductor Devices and Circuits ]

How to cite this article:
Hardik Patel, Mitesh Limachia, Purvang Dalal, Sohilkumar Dabhi, Harshit Patel, Mitul Shah. Performance Comparison of Noise-Tolerant, High- Performance CMOS Domino Logic Configurations. Journal of Semiconductor Devices and Circuits. 2025; 12(02):35-50.
How to cite this URL:
Hardik Patel, Mitesh Limachia, Purvang Dalal, Sohilkumar Dabhi, Harshit Patel, Mitul Shah. Performance Comparison of Noise-Tolerant, High- Performance CMOS Domino Logic Configurations. Journal of Semiconductor Devices and Circuits. 2025; 12(02):35-50. Available from: https://journals.stmjournals.com/josdc/article=2025/view=215542


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Regular Issue Subscription Original Research
Volume 12
Issue 02
Received 07/05/2025
Accepted 23/04/2025
Published 26/06/2025
Publication Time 50 Days
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