Power and Area – Aware Recursive Multiplier Architecture Utilizing Polymer Composites for Neural Network Acceleration

Year : 2026 | Volume : 14 | Special Issue 01 | Page : 1320 1337
    By

    Sunkara Bhanu Prakash,

  • Aravindhan Alagarsamy,

  • Pradeep C,

  • Ann Wesley Mathew,

  1. PG Scholar, Department of ECE, Koneru Lakshmaiah Education Foundation, Center for Multi -Core Architecture Computation (C – MAC), Vaddeswaram, Andhra Pradesh, India
  2. Associate Professor, Department of ECE, Koneru Lakshmaiah Education Foundation, Center for Multi – Core Architecture Computation (C – MAC), Vaddeswaram, Andhra Pradesh, India
  3. Professor, Department of ECE, Saintgits College of Engineering, Kottukulam Hills, Kottayam, Kerala, India
  4. R&D Engineer, Center for Development of Advanced Computing (CDAC), Bengaluru, Karnataka, India

Abstract

Approximate computing is widely applied in error – tolerant systems as an effective technique to enhance circuit performance by deliberately allowing occasional inaccuracies instead of strictly ensuring precise results for every computation. Among the fundamental building blocks of digital systems, multipliers play a crucial role in signal processing, control systems, and machine learning applications; however, they demand significant power, silicon area, and timing resources. Leveraging error – tolerant approximate multipliers has therefore emerged as an attractive solution for resilient applications such as multimedia processing, data analytics, image and video compression, and artificial intelligence, where perfect numerical accuracy is often not essential for acceptable system – level performance. Despite their foundational importance in digital processing hardware, conventional binary multipliers impose substantial silicon area overhead and energy consumption, which in turn restricts the scalability of high – performance and low – power systems. To overcome these challenges, this work introduces a power – and area – aware recursive multiplier architecture that efficiently exploits the principles of approximate computing. The proposed architecture further leverages the advantages of polymer composite–based electronic platforms, enabling optimized integration under strict power density and thermal constraints. The study primarily focuses on integrating the proposed recursive multiplier into neural network accelerators, where most standard multiply–accumulate operations are always executed in parallel. By significantly reducing power consumption and hardware area while preserving acceptable computational accuracy, the proposed design offers an effective and scalable solution for energy – efficient neural network inference and next – generation intelligent embedded systems.

Keywords: Approximate computing, area, binary multiplier, low power, neural network

[This article belongs to Special Issue under section in Journal of Polymer & Composites (jopc)]

How to cite this article:
Sunkara Bhanu Prakash, Aravindhan Alagarsamy, Pradeep C, Ann Wesley Mathew. Power and Area – Aware Recursive Multiplier Architecture Utilizing Polymer Composites for Neural Network Acceleration. Journal of Polymer & Composites. 2026; 14(01):1320-1337.
How to cite this URL:
Sunkara Bhanu Prakash, Aravindhan Alagarsamy, Pradeep C, Ann Wesley Mathew. Power and Area – Aware Recursive Multiplier Architecture Utilizing Polymer Composites for Neural Network Acceleration. Journal of Polymer & Composites. 2026; 14(01):1320-1337. Available from: https://journals.stmjournals.com/jopc/article=2026/view=237677


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Special Issue Subscription Original Research
Volume 14
Special Issue 01
Received 27/10/2025
Accepted 09/12/2025
Published 26/02/2026
Publication Time 122 Days
57

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