Development of polymer-based SRAM cell with enhanced low power performance

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Year : 2026 | Volume : 14 | 01 | Page :
    By

    Radhika C,

  • G.V. Ganesh,

  • Babu, P. Ashok,

  1. Research Scholar, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Andhra Pradesh, India
  2. Associate Professor, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Andhra Pradesh, India
  3. Professor, Department of Electronics and Communication Engineering, Institute of Aeronautical Engineering, Telangana, Dundigal, Hyderabad, Telangana, India

Abstract

Low-power memory technologies are in high demand with the rapid growth of portable electronics and energy-efficient computing systems. Static random-access memory (SRAM) plays a crucial role in processors, cache memories, and system-on-chip applications due to their speed and reliability. Static Random Access Memory (SRAM) is typically implemented using complementary MOS (CMOS) technology, which integrates both PMOS (P-channel Metal–Oxide–Semiconductor) and NMOS (N-channel Metal–Oxide–Semiconductor) transistors. However, as technology scales to deep submicron levels, conventional SRAM designs face challenges such as reduced stability, leakage current, and higher power consumption. Addressing these issues requires advanced SRAM cell architectures that achieve low power operation without compromising performance. This work presents the design and optimization of a polymer-based SRAM cell aimed at reducing both static and dynamic power dissipation. The approach incorporates circuit techniques and transistor-level modifications to enhance read stability, improve write ability, and minimize leakage—critical factors for reliable memory operation in low-voltage conditions. By analyzing trade-offs in cell sizing, threshold voltage adjustments, and assist techniques, the proposed design balances energy efficiency with dependable performance. Simulation results demonstrate that the improved polymer-based SRAM cell achieves substantial reductions in leakage current and overall power consumption compared to conventional cells. Moreover, the design maintains acceptable read and write margins, ensuring data integrity across varying supply voltages and process variations. Overall, the proposed polymer-based SRAM cell offers a promising solution for future low-power integrated circuits. It provides an energy-efficient memory option well-suited for high-performance CPUs, Internet of Things devices, and portable electronics where minimizing power consumption is a critical design goal.

Keywords: SRAM, PMOS, NMOS, and CMOS, Leakage current, Power consumption, Read and write margins, Energy-efficient memory, Internet of Things devices.

How to cite this article:
Radhika C, G.V. Ganesh, Babu, P. Ashok. Development of polymer-based SRAM cell with enhanced low power performance. Journal of Polymer & Composites. 2026; 14(01):-.
How to cite this URL:
Radhika C, G.V. Ganesh, Babu, P. Ashok. Development of polymer-based SRAM cell with enhanced low power performance. Journal of Polymer & Composites. 2026; 14(01):-. Available from: https://journals.stmjournals.com/jopc/article=2026/view=237667


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Ahead of Print Subscription Review Article
Volume 14
01
Received 23/09/2025
Accepted 08/10/2025
Published 26/02/2026
Publication Time 156 Days
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