Development of Polymer Based SRAM Cell with Enhance Low Power Performance

Year : 2026 | Volume : 14 | Special Issue 01 | Page : 1439 1448
    By

    Radhika C,

  • G.V. Ganesh,

  • Babu, P. Ashok,

  1. Research Scholar, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Andhra Pradesh, India
  2. Associate Professor, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Andhra Pradesh, India
  3. Professor, Department of Electronics and Communication Engineering, Institute of Aeronautical Engineering, Telangana, Dundigal, Hyderabad, Telangana, India

Abstract

Low-power memory technologies are in high demand with the rapid growth of portable electronics and energy-efficient computing systems. Static random-access memory (SRAM) plays a crucial role in processors, cache memories, and system-on-chip applications due to their speed and reliability. Static Random Access Memory (SRAM) is typically implemented using complementary MOS (CMOS) technology, which integrates both PMOS (P-channel Metal–Oxide–Semiconductor) and NMOS (N-channel Metal–Oxide–Semiconductor) transistors. However, as technology scales to deep submicron levels, conventional SRAM designs face challenges such as reduced stability, leakage current, and higher power consumption. Addressing these issues requires advanced SRAM cell architectures that achieve low power operation without compromising performance. This work presents the design and optimization of a polymer-based SRAM cell aimed at reducing both static and dynamic power dissipation. The approach incorporates circuit techniques and transistor-level modifications to enhance read stability, improve write ability, and minimize leakage—critical factors for reliable memory operation in low-voltage conditions. By analyzing trade-offs in cell sizing, threshold voltage adjustments, and assist techniques, the proposed design balances energy efficiency with dependable performance. Simulation results demonstrate that the improved polymer-based SRAM cell achieves substantial reductions in leakage current and overall power consumption compared to conventional cells. Moreover, the design maintains acceptable read and write margins, ensuring data integrity across varying supply voltages and process variations. Overall, the proposed polymer-based SRAM cell offers a promising solution for future low-power integrated circuits. It provides an energy-efficient memory option well-suited for high-performance CPUs, Internet of Things devices, and portable electronics where minimizing power consumption is a critical design goal.

Keywords: CMOS, energy-efficient memory, internet of things devices, leakage current, NMOS, PMOS, power consumption, read and write margins, SRAM.

[This article belongs to Special Issue under section in Journal of Polymer & Composites (jopc)]

How to cite this article:
Radhika C, G.V. Ganesh, Babu, P. Ashok. Development of Polymer Based SRAM Cell with Enhance Low Power Performance. Journal of Polymer & Composites. 2026; 14(01):1439-1448.
How to cite this URL:
Radhika C, G.V. Ganesh, Babu, P. Ashok. Development of Polymer Based SRAM Cell with Enhance Low Power Performance. Journal of Polymer & Composites. 2026; 14(01):1439-1448. Available from: https://journals.stmjournals.com/jopc/article=2026/view=237667


References

  1. Reddy AV, Ramalingam C, Das S, Kundu S, Majumder MK, Dhar S. Characterization of a novel low leakage power and area efficient 7T SRAM cell. In: IEEE, editor. 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems. 29th edition. Kolkata, India: IEEE; 2016. pp. 465–470.
  2. Ushma D, Bansal M. Low power, highly stable and enhanced read speed 7T SRAM. In: IEEE, editor. 2022 International Conference on Automation, Computing, and Renewable Systems. 1st edition. Pudukkottai, India: IEEE; 2022. pp. 461–466.
  3. Mohanty SP, Mishra P, Choomchuay S, Kougianos E. Statistical DOE–ILP based power–performance–process (P3) optimization of nano-CMOS SRAM. In: Mohanty SP, editor. Integration, the VLSI Journal. 45th edition. Oxford, United Kingdom: Elsevier; 2012. pp. 33–45.
  4. Mishra S, Tomar SS, Akashe S. Design low power 10T full adder using process and circuit techniques. In: IEEE, editor. 7th International Conference on Intelligent Systems and Control. 7th edition. Coimbatore, India: IEEE; 2013. pp. 11–15.
  5. Rahman MI, Bashar T, Biswas S. Performance evaluation and read stability enhancement of SRAM bit-cell in 16nm CMOS. In: IEEE, editor. 5th International Conference on Informatics, Electronics, and Vision. 5th edition. Dhaka, Bangladesh: IEEE; 2016. pp. 503–506.
  6. Moradi F, Tohidi M. Low-voltage 9T FinFET SRAM cell for low-power applications. In: IEEE, editor. 28th IEEE International System-on-Chip Conference. 28th edition. Beijing, China: IEEE; 2015. pp. 348–353.
  7. Mittal D. 6T SRAM cell design using CMOS at different technology nodes. In: IEEE, editor. 3rd Global Conference for Advancement in Technology. 3rd edition. Bangalore, India: IEEE; 2022. pp. 1–6.
  8. Premalatha C, Sarika K, Kannan PM. A comparative analysis of 6T, 7T, 8T, and 9T SRAM cells in 90nm technology. In: IEEE, editor. 2015 IEEE International Conference on Electrical, Computer, and Communication Technologies. 1st edition. Coimbatore, India: IEEE; 2015. pp. 1–5.
  9. Kapilachander T, Shanavas HI, Venkataraman V. Technical study on low power VLSI methods. In: IJI E EB, editor. International Journal of Information Engineering and Electronic Business. 4th edition. Hong Kong, China: MECS Press; 2012. pp. 60–70.
  10. Aly RE, Faisal MI, Bayoumi MA. Novel 7T SRAM cell for low power cache design. In: IEEE, editor. 2005 IEEE International SOC Conference. 1st edition. Herndon, USA: IEEE; 2005. pp. 171–174.
  11. Akashe S, Tiwari NK, Sharma R. Simulation and stability analysis of 6T and 9T SRAM cells in 45 nm era. In: IEEE, editor. 2nd International Conference on Power, Control, and Embedded Systems. 2nd edition. Allahabad, India: IEEE; 2012. pp. 1–5.
  12. Sindwani A, Saini S. A novel power efficient 8T SRAM cell. In: IEEE, editor. 2014 Recent Advances in Engineering and Computational Sciences. 1st edition. Chandigarh, India: IEEE; 2014. pp. 1–5.
  13. Moradi F, Madsen JK. Robust subthreshold 7T-SRAM cell for low-power applications. In: IEEE, editor. 2014 IEEE 57th International Midwest Symposium on Circuits and Systems. 57th edition. College Station, USA: IEEE; 2014. pp. 501–504.
  14. Emon DH, Mohammad N, Mominuzzaman SM. Design of a low standby power CNFET based SRAM cell. In: IEEE, editor. 7th International Conference on Electrical and Computer Engineering. 7th edition. Dhaka, Bangladesh: IEEE; 2012. pp. 379–382.
  15. Mishra S, Sharma V, Akashe S, Tomar SS. Design and simulation of high-level low power 7T SRAM cell using various process and circuit techniques. In: IEEE, editor. 2012 IEEE International Conference on Signal Processing, Computing, and Control. 1st edition. Solan, India: IEEE; 2012. pp. 1–6.
Special Issue Subscription Review Article
Volume 14
Special Issue 01
Received 23/09/2025
Accepted 08/10/2025
Published 26/02/2026
Publication Time 156 Days
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