A Study on Polymer-Based FinFET Applications and Logic Circuit Implementation with FinFET

Abstract

Nano devices play a crucial role in the semiconductor industry and can work as the solution for the problems like scaling of MOSFET. The FinFET can serve as the substitute of bulk CMOS in nanoscale. It mainly consists of two gate terminals which can be either shorted or kept independent.The shorted gate (SG-FinFET) configuration provides higher Ion and Ioff whereas the Independent Gate (IG-FinFET) configuration reduces the transistor count and also reduces the leakage current. Unique FinFET can be developed by proper choice of its parameters (number of fins, dimensions etc.), materials (for gate, substrate). The flexible electronics moreover has some other requirements that can be fulfilled by the polymer-based FinFET. Polymer can be used in FinFET design in two ways- as substrate and as gate material. This work elaborates the different polymer-based FinFET and their applications based on their characteristics. This paper also includes various FinFET(SG-FinFET and IG-FinFET) based basic logic circuit design such as NAND,NOR,2:1MUX,decoder ,simple Boolean simulated in LTSpice .

Browse Figures

❮ ❯

References

1. Frank DJ, Dennard RH, Nowak E, Solomon PM, Taur Y, Wong HSP “Device scaling limits of Si MOSFETs and their application dependencies”,2001. Proc IEEE 89(3):259–287.
2. Ratnesh, R.K. & Goel, Amisha & Kaushik, G & Garg, Hardik & Chandan, & Singh, Mandeep & Prasad, Binod. (2021). Advancement and challenges in MOSFET scaling. Materials Science in Semiconductor Processing. 134. 106002. 10.1016/j.mssp.2021.106002.
3. Kumar, T. & Rao, Y.. (2016). Mosfet scaling and its effects. International Journal of Pharmacy and Technology. 8. 20161-20166.
4. HaojiWan ,Xianyun Liu , Xin Su, Xincheng Ren, Shengting Luo and Qi Zhou,’ Characteristics of a Novel FinFET with Multi-Enhanced Operation Gates (MEOG FinFET)’ Appl. Sci. 2022, 12, 11279. https://doi.org/10.3390/app122111279.
5. Hisamoto, W.C.Lee,J.Bokor et al, “FinFET- A self aligneddoublegate MOSFET scalable up to 20nm”-IEEE Trans. Electronic. Devices,Vol 42, No 12, Pg 2320-2325,December 2000.
6. Ravi Shankar Pal,Savitesh Sharma and S.Dasgupta, ‘Recent Trend of FinFET Devices and its challenges:A review’,(2017),IEEE conference on Emerging Devices and smart systems(ICEDSS 2017)
7. Shekhar Verma,SumanlataTripathi,MohinderBassi,’Performance Analysis of FINFET device using Qualitative Approch for low-Power applications’,(2019) Devices for integrated Circuit(Devic),23-24 March,2019,Kalyani,India.
8. Himani Singh Rana,HimanshuSirohia,’FINFET TECHNOLOGY AN IMPROVEMENT IN VLSI TECHNOLGY’Journal of current Science vol20,special issue 02,February 2019”13th Conference”(ICOSD)
9. Mayank Shrivastava,MaryamShojaei,Dinesh Kumar Sharma,V.RamgopalRao,’A Novel Bottom Spacer FinFET Structure for improved Short-Channel,Power-Delay,and Thermal Perforance’,IEEE TRANSACTIONS ON ELECTRON DEVICES VOL.57,NO.6 JUNE 2010
10. Rajashree Das, Rupam Goswami and SrimantaBaishya “Tri-gate Hetrojunction SOI e-FinFETs.” Superlattices and Microstructure(2016), vol 19, no. 03, pages 51-61 Mar 2016
11. Brad D. Gaynor and Soha Hassoun, “Fin Shape Impact on FinFET Leakage With Application to Multithreshold and Ultralow-Leakage FinFET Design.” IEEE Transactions On Electron Device, vol. 61, no.8 pages 2738-2745 Aug 2014.
12. M. Bughio, S. DonatiGuerrieri,and G. Ghione, “Multi-gateFinFET Mixer Variability assessment through physics-basedsimulation.” IEEE Electron Device Letters vol. 38, no. 8 pages-1004-1007 Aug 2017.
13. Yao-jen lee, guang-li luo, fu-juhou, min-chengchen, chih-chao yang,chang-hongshen, wen-fa wu, jia-min shieh, and wen-kuan yeh, “GeGAA FETs and TMD FinFETs for the Applications Beyond Si—AReview.” vol. 4 no. 5 pages 286-294 Sept 2016.
14. Xin Sun, V. Moroz, N. Damrongplasit, Changhwan Shin, and Tsu-JaeKing Liu. Variation study of the planar ground-plane bulk mosfet,soiFinFET and trigate bulk mosfet designs. IEEE Transactions onElectron Devices,58(10):3294–3299, October 2011.
15. Brian Swahn and Soha Hassoun. Gate sizing: FinFETs vs 32nmbulk mosfets. In ACM/IEEE Design Automation Conference(DAC), pages 528–531, 2006.
16. J.H. van Dal, N. Collaert, G. Doombos, G. Vellianitis, G.Curatola, B.J.Pawlak, R. Duffy, C. Jonville, B. Degroote, E.Altamirano, E. Kunnen, M. Demand, S. Beckx, T. Vandeweyer, C.Delvaux, F. Leys, A. Hikavyy, R. Rooyackers, M. Kaiser,R.G.R.Weemaes, S. Biesemans, M. Jurczak, K. Anil, L. Witters, and R.J.P.Lander. Highly manufacturable FinFETs with sub-10nm fin widthand high aspect ratio fabricated with immersion lithography. In IEEE Symposium on VLSI Technology, pages 110–111, June 2007.
17. Ankit Gaurav, Sandeep S. Gill, Navneet Kaur, MunishRattan."Density gradient quantum corrections based performanceoptimization of triangular TG bulk FinFETs using ANN and GA",2016 20th International Symposium onVLSI Design and Test(VDAT), 2016
18. Jatal, Wael & Baumann, Uwe & Jacobs, Heiko &Schwierz, Frank &Pezoldt, Joerg. (2016). Tri-Gate Al0.2Ga0.8N/AlN/GaN HEMTs on SiC/Si-Substrates. Materials Science Forum. 858. 1174-1177. 10.4028/www.scientific.net/MSF.858.1174.
19. Palankovski, V., Quay, R. (2004). High Electron Mobility Transistors. In: Analysis and Simulation of Heterostructure Devices. Computational Microelectronics. Springer, Vienna. https://doi.org/10.1007/978-3-7091-0560-3_6.
20. N. A. Aadit, S. G. Kirtania, F. Afrin, Md. K. Alam, and Q. D. M. Khosru, ‘High Electron Mobility Transistors: Performance Analysis, Research Trend and Applications’, Different Types of Field-Effect Transistors - Theory and Applications. InTech, Jun. 07, 2017. doi: 10.5772/67796.
21. Ünlü, Hilmi. (2004). Modeling and Simulation of Heterojunction Bipolar Transistors. 10.1007/978-3-662-09432-7_5.
22. Sang-Hoon, Kim & Seung-Yun, Lee & Chan-Woo, Park & Jin-Young, Kang. (2005). Degradation of the SiGe hetero-junction bipolar transistor in SiGeBiCMOS process. Journal of the Korean Vacuum Society. 14.
23. Kim, Jonggook&Sadovnikov, Alexei & Menz, Philipp & Babcock, Jeff. (2012). Considerations for forward active mode reliability in an advanced hetero-junction bipolar transistor. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting. 1-4. 10.1109/BCTM.2012.6352659.
24. Chakrabartty, Chittadeepan. (2021). Study of Resonant Tunneling Diodes.
25. Hu, L.-C & Guo, W.-L & Zhang, Song-li & Liang, H.-L & Yao, S.-Y. (2006). Planar resonant tunneling diodes and their MOBILE. Tianjin DaxueXuebao (Ziran KexueyuGongcheng Jishu Ban)/Journal of Tianjin University Science and Technology. 39. 1360-1363.
26. Sun, Jian & Haddad, George & Mazumder, P. & Schulman, Joel. (1998). Resonant tunneling diodes: Models and properties. Proceedings of the IEEE. 86. 641 - 660. 10.1109/5.663541.
27. Ghosh,and S. K. Sarkar, “Performance Investigation of Nanoscale Reversible Logic gates designed with SE-TLG Approach” , International Journal of Electronics,DOI: 10.1080/00207217.2020.1756433.ISSN:13623060, 00207217,2020.
28. Ghosh, A.Jain, S. K. Sarkar, “Design and Simulation of Single Electron Threshold Logic Gate based Programmable Logic Array”,ProcediaTechnology,Volume 10,2013,Pages 866-874,ISSN 2212-0173,https://doi.org/10.1016/j.protcy.2013.12.432.
29. Ghosh, Jain, A.,S. Gharami, S.K.Sarkaret al. Small-signal model for the single-electron transistor: part I. J Comput Electron16, 296–306 (2017). https://doi.org/10.1007/s10825-017-0971-1.
30. Regeena, Mary. (2015). FinFET based switches and their application in Mechatronics. 10.1109/iNIS.2015.51.
31. Sharma,S.Dasgupta,M.VKartikeyan,FinFET for RF Applications:A Literature Review,IEEE conference on Emerging Devices and smart systems(ICEDSS 2018).
32. Girish H., ShashikumarD.R,’Insights of performance Enhancement Techniques on FinFET-based SRAM Cells.Communication on Applied Electronics(CAE)-ISSN-2594-4714Foundation of computer Science FCS,NewYork,USA Volume 5-NO.6,July 2016
33. Yash Sharma,AnushkaSingh,ArchanaPandey,’Comparative Design and Analysus of FINFET and CMOS SRAM Cell.’(2019) International Conference on singal processing and communication (ICSC)
34. Kapil Jaiswal, Prof. ShivanginiSaxena,’A review on FINFET Based SRAM Design for low Power Application’,International Journal of Technology Research and Management ISSN(online):2348-9006 vol4 Issue 5 May 2017.
35. HoomanFarkhani,AliPeiravi and Jens Madsen Kargaar,“Comparative Study of FinFETs versus 22nm Bulk CMOS technologies:SRAM Design Perspective.” System-on-Chip Conference (SOCC), 27th IEEE International, vol. 5, no. 10, pages 449-454, Nov 2016
36. P. King, X. Wu, M. Eller, S. Samavedam, M. R. Shaneyfelt, A. I.Silva, B. L. Draper, W. C. Rice, T.Meisenheimer, J. A. Felix, K. J.Shetler E. X. Zhang, T. D. Haeffner, D. R. Ball, M. L. Alles, J. S.Kauppila, L. W. Massengill, “Analysis of TID Process, Geometry,and Bias Condition Dependence in 14-nm FinFETsandImplicationsfor RF and SRAM Performance.” IEEE Transactions on NuclearScience, vol. 64, no. 1, pages 285-292, Jan 2017.
37. Venkata P. Yanambaka, Saraju P. Mohanty Elias Kougianos, DhruvaGhai, and Garima Ghai, “Process Variation Analysis andOptimization of a FinFET based VCO.” IEEE Transactions onSemiconductor Manufacturing, vol.30, no.2 pages-126-134, Feb2017.
38. Gu, J. Keane, S. Sapatnekar, and C. Kim. Width quantization awareFinFET circuit design. In IEEE Custom Integrated CircuitsConference (CICC), pages 337 –340, September 2006.
39. Greeshma Sai, N. Alivelu Manga, P. Chandra Sekhar, ‘Design and Simulation of FinFET based digital circuits for low power applications’ 2020 IEEE International Students' Conference on Electrical, Electronics and Computer Science(SCEECS), Bhopal, India, 2020, pp. 1-5, doi: 10.1109/SCEECS48394.2020.123.
40. Ramkumar E,Gracin D, Rajkamal P, BhuvanaBP,KanchanaBhaskaramVs,Design and analysis of low power and high speed FinFET based hybrid Full Adder/Substractor Circuit,2020 IEEE International Symposium on Smart Electronic System
41. GaneshKumar,Shivakumar V Gaded,Dr. Srividya P,’Power and Delay Optimization of FinFET based Adiabetic Logic SRAM Cell’
42. Hisamoto, T. Kaga, Y. Kawamoto and E. Takeda, "A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET," International Technical Digest on Electron Devices Meeting, Washington, DC, USA, 1989, pp. 833-836, doi: 10.1109/IEDM.1989.74182.
43. Kajal and Sharma Kumar Vijay, NBTI Effect Survey for Low Power Systems in Ultra-Nanoregime, Current Nanoscience 2024; 20 (3) .https://dx.doi.org/10.2174/0115734137252023230919054547.
44. K Bindu Madhavi and Suman Lata Tripathi, “Strategic Review on Different Materials for FinFET Structure Performance Optimization”,,IOP Conference Series: Materials Science and Engineering, Volume 988, International Conference on Recent Developments in Material Science and Applications (ICRDMSA 2020) 25 – 26 September 2020, Chennai, India Citation K Bindu Madhavi and Suman Lata Tripathi 2020 IOP Conf. Ser.: Mater. Sci. Eng. 988 012054
45. Torres Sevilla, Galo & Fahad, Hossain & Rojas, Jhonathan & Hussain, Aftab & Hussain, Muhammad. (2014). Flexible Nanoscale High-Performance FinFETs. ACS nano. 8. 10.1021/nn5041608.
46. Sevilla, G. A. T., Rojas, J. P., Fahad, H. M., Hussain, A. M., Ghanem, R., Smith, C. E., & Hussain, M. M. (2014). Flexible and transparent silicon‐on‐polymer based sub‐20 nm non‐planar 3D FinFET for brain‐architecture inspired computation. Advanced Materials, 26(18), 2794-2799.
47. Suman, J. V., Cheepurupalli, K. K., &Allasi, H. L. (2022). Design of Polymer‐Based Trigate Nanoscale FinFET for the Implementation of Two‐Stage Operational Amplifier. International Journal of Polymer Science, 2022(1), 3963188.
48. Mehrdad, F., & Ahangari, Z. (2022). Design and simulation of a gas sensitive junctionlessFinFET based on conducting polymer as the gate material. Physica Scripta, 97(7), 075805.
49. Dančak, C. “The FinFET: A Tutorial” , In: Goodnick, S., Korkin, A., Nemanich, R. (eds) Semiconductor Nanotechnology. Nanostructure Science and Technology. Springer, Cham. ,2018,https://doi.org/10.1007/978-3-319-91896-9_2
50. Rai, P. & Marjorie, Roji & Pavan, N.. (2016). Types of structures and advantages of FinFET. International Journal of Pharmacy and Technology. 8. 20528-20536.
51. Cartier, E. & Greene, Brian & Guo, Dechao& Wang, Gan & Wang, Yanfeng & Wong, Keith. (2015). FinFET structure and method to adjust threshold voltage in a FinFET structure.
52. Arora, Sneha & Dutta, Umesh & Kumar, Vipin. (2015). A Noise Tolerant and Low Power Dynamic Logic Circuit Using Finfet Technology. 10.13140/RG.2.1.3236.7123.
53. , Jothi & Krishna, N. (2016). FinFET Based Low Power Content Addressable Memory.
54. Hassanzadeh, Alireza &Hadidi, Sajad. (2021). Systematic approach for IG-FinFET amplifier design using gm/Id method. Analog Integrated Circuits and Signal Processing. 109. 10.1007/s10470-021-01917-9.
55. Rogers, J.A.; Bao, Z.; Baldwin, K.; Dodabalapur, A.; Crone, B.; Raju, V.R.; Kuck, V.; Katz, H.; Amundson, K.; Ewing, J.; et al. Paper-like electronic displays: Large-area rubber-stamped plastic sheets of electronics and microencapsulated electrophoretic inks. Natl. Acad. Sci. USA2001, 98, 4835–4840.
56. https://www.analog.com/en/resources/design-tools-and-calculators/ltspice-