Open Access
Priyansh Tripathi
Narendra Yadava
Mangal Deep Gupta
R.K. Chauhan
- M.Tech Student, M.M.M.U.T, Gorakhpur, Uttar Pradesh, India
- PhD Scholar, M.M.M.U.T, Gorakhpur, Uttar Pradesh, India
- PhD Scholar, M.M.M.U.T, Gorakhpur, Uttar Pradesh, India
- Professor, M.M.M.U.T, Gorakhpur, Uttar Pradesh, India
Abstract
This paper elucidates the impact of the pocket doped window on the analog performance of dual metal gate based silicon-on-insulator junctionless transistor (DMG SOIJLT). The analog parameters of the proposed SOIJLT are compared with DMG based conventional SOIJLT. The findings of analog performance comparison reveal that transconductance (gm), transconductance generation factor (TGF), output conductance (gd), output resistance (r0), intrinsic gain (AV), and cut-off frequency (fT) have improved for DMG PD-SOIJLT as compared to DMG SOIJLT. Improvements were also found in OFF-state leakage current (IOFF) and ON-OFF current ratio (ION/IOFF) for DMG PD-SOIJLT. The maximum values of gm, r0, and fT improved by 4.46 times, 3.84 times, and 3.85 times respectively, and AV improved by 21.07 times in ON-state, as compared to DMG SOIJLT. The device simulation and parameter extractions have been carried out using the SILVACO ATLAS-2D device simulator.
Keywords: Analog performance, dual metal gate (DMG), intrinsic gain, junctionless transistor (JLT),pocket doped window, silicon-on-insulator (SOI), output resistance
[This article belongs to Journal of Microelectronics and Solid State Devices(jomsd)]
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References
1. Carballo JA, Chan WT, Gargini PA, et al. ITRS 2.0: Toward a re-framing of the semiconductor technology roadmap. 2014 IEEE 32nd International Conference on Computer Design (ICCD) IEEE. Seoul, Korea. 2014, Oct. 19–22.
2. Ohno T, Kado Y, Harada M, et al. Experimental 0.25um gate fully depleted CMOS/SIMOX process using a new two-step LOCOS isolation technique. IEEE Trans, Electron Devices. Aug. 1995; 42: 1481–1486.
3. Kranti A, Yan R, Lee CW. Junctionless transistor (JNT): properties and design guidelines. 2010 Proceedings of the European Solid-State Device Research Conference. Seville, Spain. 2010, Sept. 14–16.
4. Colinge JP, Lee CW, et al. Junctionless transistors: Physics and Properties. In: Nazarov A, Colinge JP, Balestra F, Raskin JP, Gamiz F, Lysenko V. (eds.) Semiconductor-On-Insulator Materials for Nanoelectronics Applications. Engineering Materials. Berln: Springer-Verlag; 2011. pp. 187–199.
5. Colinge JP. SOI gated resistor: CMOS without junctions. Proceedings of the SOI Conference. IEEE International. Foster city, CA, USA. 2009, Oct. 5–8.
6. Vitale W. Monte Carlo study transport properties in Junctionless transistor. Proceedings of the Computational Electronic (IWCE). Pisa, Italy. IEEE. 2010, Oct. 26–29.
7. Long W, Ou H, Kuo JM, Chin KK. Dual-material gate (DMG) field effect transistor. IEEE Transactions on Electron Devices. 1999; 46(5): 865–870.
8. Shur M. Split‐gate field‐effect transistor. Applied Physics Letters. 1989; 54(2): 162–164.
9. Na KY, Kim YS. Silicon complementary metal-oxide-semiconductor field-effect transistors with dual work function gate. Japanese Journal of Applied Physics. 2006; 45(12): 9033–9036.
10. Saxena M, Haldar S, Gupta M, et al. Physics-based analytical modeling of potential and electrical field distribution in dual material gate (DMG)-MOSFET for improved hot electron effect and carrier transport efficiency. IEEE Transactions on Electron Devices. 2002; 49(11): 1928–1938.
11. Lee CW, Afzalian A, Akhavan ND, et al. Junctionless multigate field-effect transistor. Applied Physics Letters. 2009; 94(5): 053511.
12. Wagaj SC, Patil SC. Comparison study of Dual Material Gate Silicon on insulator junctionless transistor and with junction transistor for analog performance. International Journal of Materials, Mechanics and Manufacturing. 2019; 7(3): 144–149.
13. Malviya AK, Chauhan RK. Optimizing performance of dual metal gate modified source FDSOI using symmetric and asymmetric oxide spacers. International Conference on Emerging Trends in Computing and Communication Technologies (ICETCCT). Dehradun, India. 2017, Nov. 17–18.
14. Tripathi S, Mishra VK, Chauhan RK. Performance analysis of dual metal gate modified source fully depleted SOI MOSFET. i-Manager’s Journal on Embedded Systems. 2016; 5(2): 7–12.
15. Anvarifard MK. A nanoscale‐modified junctionless with considerable progress on the electrical and thermal issue. International Journal of Numerical Modelling: Electronic Networks, Devices and Fields. 2019 May; 32(3): e2537.
16. Bashir F, Murshid AM, Khanday FA, Banday MT. Impact of pocket doping on the performance of planar SOI junctionless transistor. Silicon. Jul 2020; 13(6): 1771–1776.
17. Haque Md. M, Kabir Md. H, Adnan Md. MR. Analytical modelling and verification of potential profile of DG JLFET with and without stack. International Journal of Electronics. 2021; 108(5): 819–840.
18. Sarkhel S, Bagga N, Sarkar SK. Compact 2D modeling and drain current performance analysis of a work function engineered double gate tunnel field effect transistor. Journal of Computational Electronics. 2016; 15(1): 104–114.
Journal of Microelectronics and Solid State Devices
| Volume | 8 |
| Issue | 1 |
| Received | May 1, 2021 |
| Accepted | May 20, 2021 |
| Published | May 20, 2023 |