Design and Implementation of Low-power SPI Shift Register

Year : 2023 | Volume :01 | Issue : 01 | Page : 1-15
By

C. Ramesh Kumar Reddy

Kandi Ananya

Kosike Shravani

K.K.S.S. Chaitanya

  1. Professor Department of Electronic and Communication Engineering, B.V. Raju Institute of Technology Vishnupur, Narsapur Telangana India
  2. Student Department of Electronic and Communication Engineering, B.V. Raju Institute of Technology Vishnupur, Narsapur Telangana India
  3. Student Department of Electronic and Communication Engineering, B.V. Raju Institute of Technology Vishnupur, Narsapur Telangana India
  4. Student Department of Electronic and Communication Engineering, B.V. Raju Institute of Technology Vishnupur, Narsapur Telangana India

Abstract

SPI stands for serial peripheral interface which is used for serial, synchronous and full duplex communication of data between master and slave devices. Master devices can be Microprocessors or Microcontrollers; and slaves are the Peripheral devices interfaced with them. The main internal component for architecture of master/slave block is shift register which defines its operation. But as the size of the shift register increases, power is utilized to a greater extent. So, in this project, we are going to design the shift register using CMOS, pass transistor, transmission gate and PFAL (positive feedback adiabatic logic) techniques using 90 nm technology in Synopsys Custom compiler tool and compare their performance in terms of Static power, Dynamic power, Overall power consumption, Delay and conclude with the lowest power consuming circuit which will be highly efficient to be used in low-power applications.

Keywords: SPI, shift register, CMOS, pass transistor, transmission gate, PFAL

[This article belongs to International Journal of VLSI Circuit Design & Technology(ijvcdt)]

How to cite this article: C. Ramesh Kumar Reddy, Kandi Ananya, Kosike Shravani, K.K.S.S. Chaitanya. Design and Implementation of Low-power SPI Shift Register. International Journal of VLSI Circuit Design & Technology. 2023; 01(01):1-15.
How to cite this URL: C. Ramesh Kumar Reddy, Kandi Ananya, Kosike Shravani, K.K.S.S. Chaitanya. Design and Implementation of Low-power SPI Shift Register. International Journal of VLSI Circuit Design & Technology. 2023; 01(01):1-15. Available from: https://journals.stmjournals.com/ijvcdt/article=2023/view=125879

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Regular Issue Subscription Original Research
Volume 01
Issue 01
Received July 29, 2023
Accepted August 1, 2023
Published November 6, 2023
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