Design and Simulation of LNA in 90 nm CMOS Technology for Radio Receiver using the Cadence Simulation Tool

Open Access

Year : 2022 | Volume : | Issue : 1 | Page : 1-9

    Dhananjay Nayak

  1. Student, Nirma University, Ahmedabad, Gujara, India


Due to its successful operation in the 2.4 GHz frequency region, often known as the ISM (Industrial, Scientific, and Medical) band, RFICs play a vital role in communication systems. The major parts being used transceivers for frequency translation and amplification are LNA and Mixers. Different types of mixers and LNAs are employed, and different strategies are used to optimize them. In this paper an approach for design and simulation of cascode LNA is discussed to increase to efficiency and Radio Frequency (RF) performance of LNA. More emphasis is put here on the optimization of design. The LNA parameters show how the amplifier is going to work for the proposed design. A low noise amplifier simulated in 90 nm CMOS technology. The proposed cascode LNA consists of two transistors. It exhibits 2.5-dB noise figure and 23-dB gain at 2.4 GHz while consuming only 44 nW, this results are confirmed after post layout simulations. These straightforward and analytical conclusions are particularly important since they may be used not only to build CMOS LNA circuits, and to characterise and diagnose them, whether functional prototypes or built. The Communication System’s core building block or key component is a Low Noise Amplifier. Any radio receiver is made up of a Low Noise Amplifier, a mixer, and a Filter (Power Efficient Active Filter), with the LNA playing a critical part in the circuit as an amplifier.

Keywords: Cascode low noise amplifier, LNA designing for 2.4 GHz, LNA simulation, Cadence Virtuoso simulation of LNA

[This article belongs to International Journal of Digital Communication and Analog Signals(ijdcas)]

How to cite this article: Dhananjay Nayak Design and Simulation of LNA in 90 nm CMOS Technology for Radio Receiver using the Cadence Simulation Tool ijdcas 2022; 8:1-9
How to cite this URL: Dhananjay Nayak Design and Simulation of LNA in 90 nm CMOS Technology for Radio Receiver using the Cadence Simulation Tool ijdcas 2022 {cited 2022 Jun 28};8:1-9. Available from:

Full Text PDF Download

Browse Figures


1. G. Bhushan Rao, “A high gain and high linear LNA for low power receiver front-end applications,” International Conference on Communication and Signal Processing (ICCSP), 2016.
2. Malti Bansal; Jyoti, “Cascode Inductive Source Degenerated CMOS LNA with Parallel RLC Output Matching Network for IEEE 802.11 Standard in 45 nm Technology,” Fourth International Conference on Inventive Systems and Control (ICISC), 2020.
3. Santosh B. Patil; Rajendra D. Kanphade, “Differential Input Differential Output Low Power High Gain LNA for 2.4 GHz Applications Using TSMC 180 nm CMOS RF Process,” International Conference on Computing Communication Control and Automation,2015
4. T. Johansson, “LNA Simulation using Cadence SpectreRF,” RF IC Design 2018, LinkopingUniversity
5. Li, Z., Wang, Z., Zhang, M., et al.: ‘A 2.4 GHz ultra-low-power current-reuse CG-LNA with active gm-boosting technique’, IEEE Microw. Wirel. Compon. Lett., 2014, 24, (5), pp. 348–350
6. Meaamar, A., Boon, C.C., Yeo, K.S., et al.: ‘A wideband low power lownoise amplifier in CMOS technology’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2010, 57, (4), pp. 773–782
7. Kim, Tae-Wook; Lee, Kwyro., et al.: ‘A Simple and Analytical Design Approach for Input Power Matched On-chip CMOS LNA’, JSTS: Journal of Semiconductor Technology and Science
8. Bevilacqua, A., Niknejad, A.M.: ‘An ultra-wide band CMOS low-noise amplifier 3.1–10.6-GHz wireless receivers’, IEEE J. Solid-State Circuit, 2004, 39, (12), pp. 2258–2268
9. Chen, K.H., Lu, J.H., Chen, B.J., et al.: ‘An ultra-wide band 0.4–10 GHz LNA in 0.18 μm CMOS’, IEEE Trans. Circuits Syst. II, Express Briefs, 2007, 54, (3), pp. 217–221
10. Weng, R.M., Liu, C.Y., Lin, P.C.: ‘A low-power full-band low-noise amplifier for ultra-wideband receivers’, IEEE Trans. Microw. Theory Tech., 2010, 58, (8), pp. 2077–2083
11. A. Van der Ziel, Noise in Solid State Devices and Circuits. New York: Wiley, 1986

Regular Issue Open Access Article
Volume 8
Issue 1
Received May 20, 2022
Accepted June 18, 2022
Published June 28, 2022