Spin Devices Based Area Efficient 5-Bit High Speed ADC

Open Access

Year : 2021 | Volume : | Issue : 2 | Page : 18-28

    Yogendra Kumar Upadhyaya

  1. Ashutosh Tripathi

  1. Associate Professor, Chandigarh University Mohali, Punjab, India
  2. Professor & HOD, Chandigarh University Mohali Punjab, Punjab, India


This paper uses current induced domain wall motion in a magnetic stripe and pre-charge sense amplifiers (PCSA) to design a high-speed comparator of a magnetic flash ADC. Current-induced domain-wall (DW) motion is a prominent switching mechanism promising, low power high-density and high-speed circuits. Domain-wall motion in a magnetic stripe based magnetic flash ADC (Analog to Digital Converter) is area efficient (4.84µm2) and faster compared to other ADCs. Our proposed 5-bit
Flash ADC can operate at 500MS/s with power consumption of 10.5mW. The power consumption can be further reduced to 5.06 mW by choosing a smaller step size of 10mV. By using MTJ and domain wall motion in a magnetic stripe with PCSA, SPICE compatible Verilog-A model and CMOS 45nm design kit, its performance such as power and delay have been simulated and compared with other ADCs. This design is required 0.75V supply voltage. Area is less than CMOS based ADC. Power Consumption is very low. It can work on 10mv step size.

Keywords: Domain wall motion, MTJ, Analog to Digital Converter (ADC), Spin, and Flash ADC

[This article belongs to International Journal of Applied Nanotechnology(ijan)]

How to cite this article: Yogendra Kumar Upadhyaya, Ashutosh Tripathi Spin Devices Based Area Efficient 5-Bit High Speed ADC ijan 2021; 7:18-28
How to cite this URL: Yogendra Kumar Upadhyaya, Ashutosh Tripathi Spin Devices Based Area Efficient 5-Bit High Speed ADC ijan 2021 {cited 2021 Nov 01};7:18-28. Available from: https://journals.stmjournals.com/ijan/article=2021/view=92354

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1. B. P. Ginsburg and A. P. Chandrakasan,“500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC”, IEEE Journal of Solid-State Circuits, Vol. 42, no. 4, pp.739-47, Apr.2007.
2. J. Song et al., “Evaluation of Operating Margin and Switching Probability of Voltage- Controlled Magnetic Anisotropy Magnetic Tunnel Junctions” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits vol. 4, no. 2, pp. 76-84, Dec. 2018.
3. Y. K. Upadhyaya, M. Hasan, “Energy Efficient Robust Pre-Charge Sense Amplifier,” in 2019 International Conference on Electrical, Electronics and Computer Engineering (UPCON), 2019, pp. 1–3.
4. Y. K. Upadhyaya, M. Hasan, and S. Maheshwari, “Low power and high-density magnetic flash analog to digital converter using spintronic devices and CMOS,” in 2017 International Conference on Multimedia, Signal Processing and Communication Technologies (IMPACT), 2017, pp. 237–241.
5. Y. K. Upadhyaya, M. Hasan, and S. Maheshwari, “High Speed and Low Power Sensing Amplifier based on MTJ,” in 2018 5th IEEE Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON), 2018, pp. 1–3.
6. Y. K. Upadhyaya, M. K. Gupta, M. Hasan, and S. Maheshwari, “High- Density Magnetic Flash ADC Using Domain-Wall Motion and Pre- Charge Sense Amplifiers,IEEE Trans. Magn., vol. 52, no. 6, pp. 1–10, Jun. 2016.
7. S. Parkin and S.-H. Yang, “Memory on the racetrack,” Nat. Nanotechnol., vol. 10, no. 3, pp. 195–198, Mar. 2015.
8. M. K. Gupta and M. Hasan, “A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits,” IEEE Trans. Very Large Scale Integr. Syst., vol. 24, no. 1, pp. 218–222, Jan. 2016.
9. M. K. Gupta and M. Hasan, “Robust High-Speed Ternary Magnetic Content Addressable Memory,” IEEE Trans. Electron Devices, vol. 62, no. 4, pp. 1163–1169, Apr. 2015.
10. D. Zhang, L. Zeng, Y. Zhang, J. O. Klein, and W. Zhao, “Reliability- Enhanced Hybrid CMOS/MTJ Logic Circuit Architecture,” IEEE Trans. Magn., vol. 53, no. 11, pp. 1–5, Nov. 2017.
11. Paritosh Sharma, Y. K. Upadhyaya, Kshetra Singh “Design of Ultra Low-Power Robust SRAM Cell” Nano Trends: A Journal of Nanotechnology and its Application, Volume 21, Issue2, 2019, pp.7-18, ISSN:0973-418X(Online).
12. S.Ikeda et al., “Tunnel magnetoresistance of 604% at 300 Kb suppression of Ta diffusion in CoFeB/MgO/CoFeB pseudo-spin-valves annealed at high temperature,” Appl. Phys. Lett., vol. 93, no. 8, p. 082508, Aug. 2008.
13. S. Parkin and S.-H.Yang, “Memory on the racetrack,” Nature Nanotechnol., vol. 10, pp. 195–198, Mar. 2015.
14. Weisheng Zhao, C. Chappert, V. Javerliac, and J.-P. Noziere, “High Speed, High Stability and Low Power Sensing Amplifier for MTJ/CMOS Hybrid Logic Circuits,” IEEE Trans. Magn., vol. 45, no. 10, pp. 3784–3787, Oct. 2009.
15. W. Zhao, J. Duval, J.-O. Klein, and C. Chappert, “A compact model for magnetic tunnel junction (MTJ) switched by thermally assisted Spin transfer torque (TAS + STT),” Nanoscale Res. Lett., vol. 6, no. 1, pp. 368, Apr. 2011.
16. E. Deng, Y. Zhang, J.-O. Klein, D. Ravelsona, C. Chappert, and W. Zhao, “Low Power Magnetic Full-Adder Based on Spin Transfer Torque MRAM,” IEEE Trans. Magn., vol. 49, no. 9, pp. 4982–4987, Sep. 2013.
17. M. Sharad and K. Roy, “Spintronic switches for ultralow energy on-chip and inter-chip current-mode interconnects,” IEEE Electron Device Lett., vol. 34, no. 8, pp. 1068–1070, Aug. 2013.
18. Y. Zhang, W.S. Zhao, “Perpendicular-Magnetic-anisotropy CoFeB racetrack memory” Journal of applied physics 111, May 2012.
19. E. Atoofian, “Reducing shift penalty in domain wall memory through register locality,” In Proceedings of the 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES ’15). IEEE Press, Piscataway, NJ, USA, pp.177-186, Oct.2015.
20. Y.J.Min, A.Abdullah, H.K.Kim, S.W.Kim A 5-bit 500-MS/s time-domain flash ADC in 0.18-μm CMOS Integrated Circuits (ISIC), 2011 13th International Symposium on,Dec.2011.
21. J. E. Proesel and L. T. Pileggi, “”A 0.6-to-1V inverter based 5-bit flash ADC in 90nm digital CMOS,”” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), pp.153-56, Sep.2008

Regular Issue Open Access Article
Volume 7
Issue 2
Received September 22, 2021
Accepted October 26, 2021
Published November 1, 2021