Spin Devices Based Area Efficient 5-Bit High Speed ADC

Open Access

Year : 2021 | Volume : | Issue : 2 | Page : 18-28
By

    Yogendra Kumar Upadhyaya

  1. Ashutosh Tripathi

  1. Associate Professor, Chandigarh University Mohali, Punjab, India
  2. Professor & HOD, Chandigarh University Mohali Punjab, Punjab, India

Abstract

This paper uses current induced domain wall motion in a magnetic stripe and pre-charge sense amplifiers (PCSA) to design a high-speed comparator of a magnetic flash ADC. Current-induced domain-wall (DW) motion is a prominent switching mechanism promising, low power high-density and high-speed circuits. Domain-wall motion in a magnetic stripe based magnetic flash ADC (Analog to Digital Converter) is area efficient (4.84µm2) and faster compared to other ADCs. Our proposed 5-bit
Flash ADC can operate at 500MS/s with power consumption of 10.5mW. The power consumption can be further reduced to 5.06 mW by choosing a smaller step size of 10mV. By using MTJ and domain wall motion in a magnetic stripe with PCSA, SPICE compatible Verilog-A model and CMOS 45nm design kit, its performance such as power and delay have been simulated and compared with other ADCs. This design is required 0.75V supply voltage. Area is less than CMOS based ADC. Power Consumption is very low. It can work on 10mv step size.

Keywords: Domain wall motion, MTJ, Analog to Digital Converter (ADC), Spin, and Flash ADC

[This article belongs to International Journal of Applied Nanotechnology(ijan)]

How to cite this article: Yogendra Kumar Upadhyaya, Ashutosh Tripathi Spin Devices Based Area Efficient 5-Bit High Speed ADC ijan 2021; 7:18-28
How to cite this URL: Yogendra Kumar Upadhyaya, Ashutosh Tripathi Spin Devices Based Area Efficient 5-Bit High Speed ADC ijan 2021 {cited 2021 Nov 01};7:18-28. Available from: https://journals.stmjournals.com/ijan/article=2021/view=92354

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Regular Issue Open Access Article
Volume 7
Issue 2
Received September 22, 2021
Accepted October 26, 2021
Published November 1, 2021