Editor’s Profile

Name: Dr. Shafi Qureshi

Editor : Journal of VLSI Design Tools and Technology

Email:

Affiliation: Indian Institute of Technology, Kanpur, Uttar Pradesh, India 208016

Institutional Profile Link : http://home.iitk.ac.in/~qureshi/

Professor in Department of Electrical Engineering at Indian Institute of Technology, Kanpur, Uttar Pradesh, India
My expertise are Electrical Engineering

Recent Publications

  1. S. Sharma, C. Shekhar and S. Qureshi, “ASIC Implementation of UART chip having 16 Baud Rates at SCL 180 nm Technology Node,” 2022 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), Bangalore, India, 2022, pp. 1-6, doi: 10.1109/CONECCT55679.2022.9865854
  2. C. Shekhar and S. Qureshi, “Design of 50 MHz PLL using indigenous SCL 180 nm CMOS Technology,” 2021 IEEE International Symposium on Smart Electronic Systems (iSES), Jaipur, India, 2021, pp. 12-17, doi: 10.1109/iSES52644.2021.00016
  3. S. Sharma and S. Qureshi, “Simulation Study: Process, Device and Circuit Implementation of Tubs in the BOX (TBOX) cSiGe PMOSFET having low Off State Leakage Current,” 2022 IEEE Delhi Section Conference (DELCON), New Delhi, India, 2022, pp. 1-6, doi: 10.1109/DELCON54057.2022.9753432
  4. Shruti Mehrotra, S. Qureshi. Insight into Potential Well Based Nanoscale FDSOI MOSFET Using Doped Silicon Tubs- A Simulation and Device Physics Based Study: Part I: Theory and Methodology. Physics. 2020; https://doi.org/10.48550/arXiv.2007.02270.11
  5. C. K. Jaiswal, Nishant, S. Mehrotra and S. Qureshi, “Proposed Process Flow for Potential Well Based FDSOI MOSFET at 20 nm Gate Length,” 2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Penang, Malaysia, 2020, pp. 1-3, doi: 10.1109/EDTM47692.2020.9117868