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M Krishna Vamsi,
K Lakshman Teja,
R Yeswanth Narayana,
K Bhaskara Sai Srivardhan,
Ms. K Siva Ranjini,
- UG Scholar, Department of Electronics and Communication Engineering, Bonam Venkata Chalamayya Engineering College (Autonomous),Odalarevu, Andhra Pradesh, India
- UG Scholar, Department of Electronics and Communication Engineering, Bonam Venkata Chalamayya Engineering College (Autonomous),Odalarevu, Andhra Pradesh, India
- UG Scholar, Department of Electronics and Communication Engineering, Bonam Venkata Chalamayya Engineering College (Autonomous),Odalarevu, Andhra Pradesh, India
- UG Scholar, Department of Electronics and Communication Engineering, Bonam Venkata Chalamayya Engineering College (Autonomous),Odalarevu, Andhra Pradesh, India
- Assistant Professor, Department of Electronics and Communication Engineering, Bonam Venkata Chalamayya Engineering College (Autonomous), Andhra Pradesh, India
Abstract
This Paper focuses on the design and implementation of a Coffee Machine using Verilog, aimed at understanding how real-life machines can be controlled using digital logic. In daily life, a coffee machine works by taking user inputs, processing them, and giving the required output such as preparing coffee. The main objective of this project is to design a simple digital system that controls the basic working of a coffee machine. The design is created using Verilog Hardware Description Language, where different states of the coffee machine such as idle, taking input, preparing coffee, and dispensing coffee are modeled using digital logic. Simple control signals are used to represent actions like starting the machine, selecting coffee, and completing the process. This approach helps beginners understand how hardware behaves step by step in a real-world system. The design is tested and verified using simulation, which confirms that the coffee machine works correctly for all inputs. Furthermore, the design highlights modularity and scalability, facilitating future improvements like multiple beverage options, timing control, and user interface integration. Additionally, it familiarizes students with practical elements of designing digital systems, such as state optimization and resource efficiency. The project highlights include easy understanding, real- life relevance, and clear control flow, making it suitable for beginners. Overall, the project demonstrates how everyday machines can be represented and controlled using simple hardware logic.
Keywords: Verilog HDL, Automatic Coffee Machine, Digital Logic Design, Finite State Machine (FSM), FPGA Implementation
M Krishna Vamsi, K Lakshman Teja, R Yeswanth Narayana, K Bhaskara Sai Srivardhan, Ms. K Siva Ranjini. AUTOMATIC COFEEE MAKING MACHINE USING VERILOG HDL. Journal of Electronic Design Technology. 2026; 17(01):-.
M Krishna Vamsi, K Lakshman Teja, R Yeswanth Narayana, K Bhaskara Sai Srivardhan, Ms. K Siva Ranjini. AUTOMATIC COFEEE MAKING MACHINE USING VERILOG HDL. Journal of Electronic Design Technology. 2026; 17(01):-. Available from: https://journals.stmjournals.com/joedt/article=2026/view=239596
References
[1] Arumilli VS, Ghatta AK, Megalingam RK. FPGA–Controlled Automated Coffee Maker using Verilog. In2024 Third International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT) 2024 Jul 24 (pp. 1-7). IEEE.
[2] Fuad MH, Yeassin R, Hassan KM, Sykot MM, Nayan MF. Design of a Vending Machine Using Verilog HDL and Implementation in Genus & Encounter. European Journal of Electrical Engineering and Computer Science. 2023 Dec 29;7(6):88-95.
[3] Verilog HDL and Implementation in Genus & Encounter,” European Journal of Electrical Engineering and Computer Science, vol. 7, no. 6, pp. 88–95, 2023.
[4] Chidananda Datta P, Vinay Kumar C, Singh R, Mummaneni K. Optimized RTL design of a vending machine through FSM using verilog HDL. InMicro and Nanoelectronics Devices, Circuits and Systems: Select Proceedings of MNDCS 2022 2022 Sep 12 (pp. 305-316). Singapore: Springer Nature Singapore.
[5] Vishwas AP, Addala VV, Megalingam RK. Vending machine for water using verilog. In2023 4th IEEE Global Conference for Advancement in Technology (GCAT) 2023 Oct 6 (pp. 1-5). IEEE.
[6] Singh R, Sai K, Reddy M, Kalyan Y, Pendela R, Upadhyay S. Design and Optimization of FPGA-Based Vending Machine. InRecent Advances in Artificial Intelligence for Sustainable Development (RAISD 2025) 2025 Jul 17 (pp. 77-87). Atlantis Press.
[7] Das N, Mandal R, Mitra A, Maiti B, Nandy S, Datta D. FPGA Based Vending Machine. International Journal of Scientific Research in Computer Science, Engineering and Information Technology. 2018:1533-7.
[8] Rakshith S, Niranjana S. User-friendly Vending Machines: A Moore FSM Perspective. In2024 5th IEEE Global Conference for Advancement in Technology (GCAT) 2024 Oct 4 (pp. 1-6). IEEE.
[9] Mahambrey AA, Pasyanthi P. IntelliVend Algorithm Based FSM Model for Book Vending Machine. In2026 7th International Conference on Mobile Computing and Sustainable Informatics (ICMCSI) 2026 Jan 7 (pp. 1912-1917). IEEE.
[10] Verma R. Switching Rate Activity Monitoring at RTL and Synthesis Level for Circuit Integrity. The Ohio State University; 2023.
[11] Soysal M, Koliogeorgi K, Firtina C, Ghiasi NM, Nadig R, Mao H, de Oliveira Junior GF, Liang Y, Zambaku K, Sadrosadati M, Mutlu O. MARS: Processing-in-memory acceleration of raw signal genome analysis inside the storage subsystem. InProceedings of the 39th ACM International Conference on Supercomputing 2025 Jun 8 (pp. 513-534).
Journal of Electronic Design Technology
| Volume | 17 |
| 01 | |
| Received | 30/03/2026 |
| Accepted | 31/03/2026 |
| Published | 02/04/2026 |
| Publication Time | 3 Days |
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