MAC Unit Implementation on FPGA

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This is an unedited manuscript accepted for publication and provided as an Article in Press for early access at the author’s request. The article will undergo copyediting, typesetting, and galley proof review before final publication. Please be aware that errors may be identified during production that could affect the content. All legal disclaimers of the journal apply.

Year : 2026 | Volume : 13 | 01 | Page :
    By

    Dnyaneshwari L. Shinde,

  • Alisha B. Mulani,

  1. Student, Electronics & Telecommunication, SKN Sinhgad College of Engineering, Pandharpur, Maharashtra, India
  2. Student, Electronics & Telecommunication, SKN Sinhgad College of Engineering, Pandharpur, Maharashtra, India

Abstract

Multiply–accumulate (MAC) computations account for a large part of machine learning accelerator operations. The pipelined structure is usually adopted to improve the performance by reducing the length of critical paths. An increase in the number of flip-flops due to pipelining, however, generally results in significant area and power increase. Using this method, we create and build a cutset-free feedforward MAC architecture that maximizes data propagation and removes superfluous pipeline registers. By reorganizing the computation flow to eliminate unnecessary dependencies, the suggested MAC unit permits continuous forward data movement without compromising correctness. In order to achieve high operating speed with low latency, pipeline and parallel processing techniques are combined to guarantee that intermediate results propagate smoothly across stages. The suggested architecture, in contrast to conventional designs, minimizes register insertion and prevents over-pipelining, resulting in a more area- and power-efficient implementation. A large number of flip-flops are often required to meet the feedforward-cutset rule. Based on the observation that this rule can be relaxed in machine learning applications, we propose a pipelining method that eliminates some of the flip-flops selectively. The simulation show that the proposed MAC unit achieved a 50% area reduction compared with the conventional pipelined MAC. In this work, we propose and implement a cutset-free feedforward MAC unit that eliminates redundant dependencies and optimizes data flow for high-speed and low-latency operation. The architecture leverages pipeline and parallel processing techniques to ensure continuous data propagation without stalling, thereby maximizing throughput.

Keywords: Feedforward, Cutset-Free, Multiply-Accumulate (MAC) Unit, FPGA Implementation, Low-Latency, High-Speed Computing, Digital Signal Processing (DSP), Parallel Processing, Power Efficiency.

How to cite this article:
Dnyaneshwari L. Shinde, Alisha B. Mulani. MAC Unit Implementation on FPGA. Journal of Microcontroller Engineering and Applications. 2026; 13(01):-.
How to cite this URL:
Dnyaneshwari L. Shinde, Alisha B. Mulani. MAC Unit Implementation on FPGA. Journal of Microcontroller Engineering and Applications. 2026; 13(01):-. Available from: https://journals.stmjournals.com/jomea/article=2026/view=238854


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Ahead of Print Subscription Review Article
Volume 13
01
Received 16/07/2025
Accepted 05/12/2025
Published 19/03/2026
Publication Time 246 Days
30

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