The Role of Majority Functions in Enhancing Full Subtractor Performance in High-Density Logic Circuits

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Year : August 17, 2024 at 4:19 pm | [if 1553 equals=””] Volume : [else] Volume :[/if 1553] | [if 424 equals=”Regular Issue”]Issue[/if 424][if 424 equals=”Special Issue”]Special Issue[/if 424] [if 424 equals=”Conference”][/if 424] : | Page : –

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Angshuman Chakraborty, Tanmoy Baraj,

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  1. Associate Professor, M.Tech Scholar Department of Electronics and Telecommunication Engineering, TIT, Narsingh, Department of Electronics and Telecommunication Engineering, TIT, Narsingh Madhya Pradesh, Madhya Pradesh India, India
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Abstract

nIn the present trend of very large-scale integration (VLSI) technology, implementing a Boolean function with the fewest number of gates (logic) has always been important. Low power design strategies now provide much more benefits than in the past. Performance, affordability, and dependability may be key issues in this area of technology design. Power dissipation is now recognized as a crucial component in the development of competitive market areas such wireless applications, laptops, and portable medical equipment. In this paper, we have compared multiple full subtractor circuits for their total transistor count and overall power consumption. We have proposed a majority function based full subtractor and compared the same with the existing one. The proposed circuit shows some substantial benefits over its existing counterpart.

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Keywords: VLSI, Majority function, Leakage Power, MTCMOS, Threshold.

n[if 424 equals=”Regular Issue”][This article belongs to Journal of Semiconductor Devices and Circuits(josdc)]

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[/if 424][if 424 equals=”Special Issue”][This article belongs to Special Issue under section in Journal of Semiconductor Devices and Circuits(josdc)][/if 424][if 424 equals=”Conference”]This article belongs to Conference [/if 424]

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How to cite this article: Angshuman Chakraborty, Tanmoy Baraj. The Role of Majority Functions in Enhancing Full Subtractor Performance in High-Density Logic Circuits. Journal of Semiconductor Devices and Circuits. August 4, 2024; ():-.

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How to cite this URL: Angshuman Chakraborty, Tanmoy Baraj. The Role of Majority Functions in Enhancing Full Subtractor Performance in High-Density Logic Circuits. Journal of Semiconductor Devices and Circuits. August 4, 2024; ():-. Available from: https://journals.stmjournals.com/josdc/article=August 4, 2024/view=0

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References

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  1. A new design of adder circuit for low power and high speed in sub-threshold region [Angshuman Chakraborty, and Sambhu Nath Pradhan. International Journal of Electronics Letters1 (2014): 17-29.]
  2. VLSI design of full subtractor using Multi-Threshold CMOS to reduce the leakage power and ground bounce noise. : [ISSN (PRINT): 2393‐8374, (ONLINE): 2394‐0697,VOLUME‐2, ISSUE‐2,2015 ,Pawar Chander & Pokala Santosh.
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  4. Area efficient Full Subtractor design using CMOS Technology. : [SSN (PRINT) : 2320 – 8945, Volume -2, Issue -4, 2014 Monikashree T.S , Divya A , Kesthara V , Nithya Shree S
  5. Novel Energy Efficient one bit Full Subtractor at 65nm technology [Basha, M. Mahaboob, K. Venkata Ramanaiah, and P. Ramana Reddy. [2015 International Conference on Electrical, Electronics, Signals, Communication and Optimization (EESCO). IEEE, 2015.
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  7. High performance full subtractor using floating-gate MOSFET [Gupta, Roshani, Rockey Gupta, and Susheel Sharma. Microelectronic Engineering162 (2016): 75-78.]
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[if 424 not_equal=””][else]Ahead of Print[/if 424] Subscription Original Research

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Volume
[if 424 equals=”Regular Issue”]Issue[/if 424][if 424 equals=”Special Issue”]Special Issue[/if 424] [if 424 equals=”Conference”][/if 424]
Received July 9, 2024
Accepted July 17, 2024
Published August 4, 2024

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