Open Access
Anusha Bhanu
Rajesh Odela
G.R. Padmini
- Assistant Professor Vasavi College of Engineering Hyderabad, Telangana India
- Associate Professor Vasavi College of Engineering Hyderabad, Telangana India
- Associate Professor Vasavi College of Engineering Hyderabad, Telangana India
Abstract
FIFO (first in first out) is a memory array in which the data written first into the memory will be read first with the help of the control signals read and write where the control signal write is used to write the data into the memory and the control signal read is used to read the data from the memory. To avoid the memory overflow and to know that whether there is a space in memory to write, a few status signals are asserted which are empty and full. The empty signal is high which means that all the memory location in the FIFO is empty i.e., no data written is into it and if the full signal is high then all the memory location in the FIFO is occupied with some data. The FIFO has been designed with a depth of 64 locations and the size of each location is 16-bit and verify it with the help of System Verilog-based UVM (universal verification methodology). The coverage driven verification is being used to verify the design functional accuracy. Constrained randomization has been used to attain the maximum amount of coverage (i.e., both code coverage and functional coverage). Code coverage of 99.43% and functional coverage of 100% have been achieved.
Keywords: Code coverage, design and verification, functional coverage, synchronous FIFO
References
1. Akhare Mohini, Narkhede Nitin. Design and verification of generic FIFO using layered test bench and assertion technique. International Journal of Engineering and Advanced Technology (IJEAT). 2019; 8(6): 5254–5260.
2. Vinoth Nagarajan. The design and verification of a synchronous first-in-first-out (FIFO) module using system verilog based universal verification methodology (UVM). [Master’s Project]. New York: Rochester Institute of Technology. 2018.
3. Morris Mano, Emeritus, Michael D. Digital Design: with an Introduction to the Verilog HDL. 5th ed. Pearson Education: Uttar Pradesh, India: January 2013.
4. Bergeron Janick. Writing Testbenches Using System Verilog. Berlin, Germany: Springer; 2006.
5. Maurya Shilpa. Design of RTL synthesizable 32-Bit FIFO memory. International Journal of Engineering Research & Technology (IJERT). 2016; 5(11): 591–593.
6. Bergeron Janick. Writing Testbenches: Functional Verification of HDL Models. Germany: Springer; 2003.
7. Samir Palnitkar. Verilog HDL: A Guide to Digital Design and Synthesis. 2nd ed. Hoboken, New Jersey: Prentice Hall PTR; 2003.
8. Navaid Zafar Rizvi, Rajat Arora. Implementation and verification of synchronous FIFO using system verilog verification methodology. Journal of Communications Technology, Electronics and Computer Science. 2015; 2: 18.
9. Amit Kumar, Shankar, Neeraj Sharma. Verification of asynchronous FIFO using system. International Journal of Computer Applications. 2014; 86(11): 0975–8887.
10. Mehta Ashok B. System Verilog Assertions and Functional Coverage. 2nd ed. New York: Springer Verlag; 2013.
Recent Trends in Electronics Communication Systems
| Volume | |
| Received | March 12, 2021 |
| Accepted | April 10, 2021 |
| Published | April 10, 2023 |