Design and Implementation of a 4-Bit Breadboard CPU Using Digital Integrated Circuits

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This is an unedited manuscript accepted for publication and provided as an Article in Press for early access at the author’s request. The article will undergo copyediting, typesetting, and galley proof review before final publication. Please be aware that errors may be identified during production that could affect the content. All legal disclaimers of the journal apply.

Year : 2026 | Volume : 17 | 02 | Page :
By

Aditya Chauhan,

Shrushti Amin,

Himanshu Prajapati,

Purvang Dalal,

  1. Student, Department of Electronics and Communication, Dharmsinh Desai University, Nadiad, Gujarat, India
  2. Student, Department of Electronics and Communication, Dharmsinh Desai University, Nadiad, Gujarat, India
  3. Faculty Guide, Department of Electronics and Communication, Dharmsinh Desai University, Nadiad, Gujarat, India
  4. Faculty Guide, Department of Electronics and Communication, Dharmsinh Desai University, Nadiad, Gujarat, India

Abstract

This paper presents the design and hardware realization of a simple 4-bit CPU built using discrete TTL integrated circuits on a breadboard. The CPU employs a 4-bit common data bus with tri-state buffers for device arbitration, three 4-bit registers (Register A, Register B, and an Output Register) implemented with 74LS175 quad D flip-flops, and a 4-bit ALU for addition/subtraction using a 74LS83 adder and XOR gates. Manual control signals (load, en- able, add/sub, etc.) and DIP switch inputs allow step-by-step operation under a hand-driven clock pulse. The system was first verified in simulation and then tested on a physical proto- type. Experiments confirmed correct execution of register load, register-to-register transfer, add, and subtract operations across multiple test cases, with results validated against expected values on the LED output array. Beyond the specific hardware result, the project is framed as a self-contained pedagogical case study: every design decision, from the choice of a shared tri-state bus to the reuse of a single adder for both addition and subtraction, is made deliber- ately visible and traceable to a single hand-clocked step, so that a learner can connect abstract register-transfer-level concepts directly to measurable electrical behaviour. The reported test cases, spanning ordinary operation, zero operands, and deliberate overflow/underflow condi- tions, are intended to serve as a compact, reproducible verification checklist for similar low- cost, breadboard-scale processor builds, and the resulting datapath is explicitly positioned as a reusable foundation for the automated, control-unit-driven extension discussed later in the paper.

Keywords: 4-bit CPU, Breadboard implementation, Tri-state buffers, ALU, TTL circuits, Digital design

How to cite this article: Aditya Chauhan, Shrushti Amin, Himanshu Prajapati, Purvang Dalal. Design and Implementation of a 4-Bit Breadboard CPU Using Digital Integrated Circuits. Journal of Electronic Design Technology. 2026; 17(02):-.
How to cite this URL: Aditya Chauhan, Shrushti Amin, Himanshu Prajapati, Purvang Dalal. Design and Implementation of a 4-Bit Breadboard CPU Using Digital Integrated Circuits. Journal of Electronic Design Technology. 2026; 17(02):-. Available from: https://journals.stmjournals.com/joedt/article=2026/view=250807

References

  1. Hennessy JL, Patterson DA. Computer architecture: a quantitative approach. Elsevier; 2011 Oct 7.
  2. Rabaey JM, Chandrakasan A, Nikolic B. Digital integrated circuits. Englewood Cliffs: Prentice hall; 2002 Dec.
  3. Patterson DA. Reduced instruction set computers. Communications of the ACM. 1985 Jan 2;28(1):8-21.
  4. Kumamaru N. Students experiment to construct a 4bit CPU. In2022 IEEE International Conference on Mechatronics and Automation (ICMA) 2022 Aug 7 (pp. 152-156). IEEE.
  5. Sklar B. Digital communications: fundamentals and applications. Pearson; 2021 Jan 27.
  6. Leach N. Digital Design: Principles and Practices. Michael D. Chiletti, M. Morris Mano–” Quizlet. 2021.
  7. Rafiquzzaman M. Fundamentals of digital logic and microcomputer design. John Wiley & Sons; 2005 Jun 6.
  8. Null L, Lobur J. The essentials of computer organization and architecture. Jones & Bartlett Publishers; 2014 Feb 17.
  9. Stallings W. Computer organization and architecture: designing for performance. Pearson Education India; 2016.
  10. Tamir Y, Tremblay M. High-performance fault-tolerant VLSI systems using micro rollback. IEEE transactions on Computers. 1990 Apr 30;39(4):548-54.
  11. Newman KE, Hamblen JO, Hall TS. An introductory digital design course using a low- cost autonomous robot. IEEE Transactions on Education. 2002 Nov 7;45(3):289-96.
  12. Wang G. Bridging the gap between textbook and real applications: A teaching methodology in digital electronics education. Computer Applications in Engineering Education. 2011 Jun;19(2):268-79.
  13. Yunten T, inventor. Yunten model computer system and lab kit for education. United States patent US 8,480,398. 2013 Jul 9.
  14. Rodriguez BJ. A minimal TTL processor for architecture exploration. InProceedings of the 1994 ACM symposium on applied computing 1994 Apr 6 (pp. 338-340).
  15. Bailey C, Freeman MJ. A java bread-board simulator: Digital circuit simulation with an open-source toolset. IADIS International Journal on Computer Science and Information System. 2010;55(1):13-25.
  16. Mano MM, Ciletti MD. Digital design: With an introduction to the Verilog HDL, VHDL, and SystemVerilog. (No Title). 2018.
  17. Wolford BJ, Hui CS, Venkatramani K, inventors; International Business Machines Corp, Motorola Inc, assignee. Tri-state bus contention circuit preventing false switching caused by poor synchronization. United States patent US 6,134,620. 2000 Oct 17.
  18. Rinku R, Dahiya P. Advance high performance bus arbitration techniques (AHB): A state-of-the-art review. IOSR Journal of VLSI and Signal Processing. 2017;7:51-6.
  19. Nisan N, Schocken S. The elements of computing systems: building a modern computer from first principles. MIT press; 2021 Jun 15.
  20. Nair VS, Nair AS. Exploring Abstractions of a General-Purpose Computer by Developing a Mini Breadboard Computer. In2018 4th International Conference for Convergence in Technology (I2CT) 2018 Oct 27 (pp. 1-4). IEEE.
  21. Doğan M, Öztoprak K, Tolun MR. Teaching computer architecture by designing and simulating processors from their bits and bytes. PeerJ Computer Science. 2024 Feb 19;10:e1818.
  22. Doğan M, Öztoprak K, Tolun MR. Teaching computer architecture by designing and simulating processors from their bits and bytes. PeerJ Computer Science. 2024 Feb 19;10:e1818.
Ahead of Print Subscription Review Article
Volume 17
02
Received 15/07/2026
Accepted 20/07/2026
Published 27/07/2026
Publication Time 12 Days

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