Design and Implementation of 256-bit Vedic Multiplier on Reconfigurable Platform

Year : 2025 | Volume : 15 | Issue : 03 | Page : 56 65
    By

    Dr. Altaf Mulani,

  1. Professor & Head, Department of Electronics & Telecommunication Engineering, SKN Sinhgad College of Engineering, Korti, Maharashtra, India

Abstract

Multiplication is a fundamental arithmetic operation in digital signal processing and embedded systems. Traditional multiplier architectures often suffer from increased latency and resource utilization when scaled to higher bit widths. Vedic Mathematics, an ancient Indian technique, offers a novel and efficient alternative. This paper presents the design and implementation of a 256-bit Vedic multiplier using the Urdhva Tiryakbhyam Sutra on a reconfigurable hardware platform, specifically FPGA. The proposed architecture decomposes the 256-bit multiplication into smaller 64-bit and 32-bit blocks using a hierarchical recursive approach. The multiplier is modeled using VHDL and synthesized on a Xilinx Artix-7 FPGA using Vivado. The modular design enables parallel computation, significantly improving speed and scalability. Results indicate a substantial reduction in critical path delay and LUT utilization compared to conventional array and Booth multipliers. The 256-bit Vedic multiplier achieved a maximum operating frequency of 156 MHz with a resource utilization efficiency of over 70%. Comparative analysis with existing designs showcases a 30% improvement in speed and a 25% reduction in area. The proposed method not only demonstrates the capability of Vedic mathematics in high-bit-width arithmetic but also highlights its suitability for reconfigurable hardware implementations where efficiency is paramount. This work lays a strong foundation for incorporating Vedic arithmetic in cryptographic processors, DSP engines, and high-performance computing systems.

Keywords: Vedic Multiplier, Urdhva Tiryakbhyam Sutra, FPGA, High-Speed Arithmetic, Reconfigurable Architecture

[This article belongs to Journal of Materials & Metallurgical Engineering ]

How to cite this article:
Dr. Altaf Mulani. Design and Implementation of 256-bit Vedic Multiplier on Reconfigurable Platform. Journal of Materials & Metallurgical Engineering. 2025; 15(03):56-65.
How to cite this URL:
Dr. Altaf Mulani. Design and Implementation of 256-bit Vedic Multiplier on Reconfigurable Platform. Journal of Materials & Metallurgical Engineering. 2025; 15(03):56-65. Available from: https://journals.stmjournals.com/jomme/article=2025/view=230585


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Regular Issue Subscription Review Article
Volume 15
Issue 03
Received 11/07/2025
Accepted 29/10/2025
Published 06/11/2025
Publication Time 118 Days
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