Design and Implementation of High-Speed Low Power Low Area Hybrid One Bit Full Adder Using CMOS Technology

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Year : June 14, 2024 at 12:52 pm | [if 1553 equals=””] Volume :01 [else] Volume :01[/if 1553] | [if 424 equals=”Regular Issue”]Issue[/if 424][if 424 equals=”Special Issue”]Special Issue[/if 424] [if 424 equals=”Conference”][/if 424] : 02 | Page : 29-39

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Vannala Sowmya, P. Sumithabhashini

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  1. Student, Professor Department of Electronics and Communication Engineering, Holy Mary Institute of Technology and Science, Bogaram (v), Keesara, Department of Electronics and Communication Engineering, Holy Mary Institute of Technology and Science, Bogaram (v), Keesara Hyderabad, Hyderabad India, India
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Abstract

nIn this article, we’ll take a look at a new kind of Full Adder (FA) design that mixes traditional Complementary Metal Oxide Semiconductors (CCMOS) with Pass Transistors (PTs) and Transmission Gates (TGs). To analyze the circuit’s performance, we used the Mentor Graphics software package. Since all twenty (20) varieties of Full Adder circuits were able to be measured and compared, this research was conducted. When the clock rate of the microprocessor’s ALU increases, FA efficiency must be enhanced. These results can be used to create state-of-the-art hybrid FAs with static CMOS logic, PTs, and TGs. Without the Cadence 45 nm toolkit, the FA would not exist. The reliability of the system was tested with twenty FA designs running from 0.4 V to 1.2 V. The proposed FA has been modified so that words of up to 64 bits in length may be used. The suggested FA is one of just six current systems that can continue operating at 64 bits without intermediate phase buffering. Results from simulations showing very low power usage and delay lend weight to the suggested architecture. The suggested hybrid FA circuit is a viable option for the data route design of contemporary high-performance CPUs, as shown by the simulation results. Using Mentor 16nm Technology, we successfully prototyped and tested a one-bit complete adder.

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Keywords: FA, CCMOS, ALU, Microprocessor, CMOS, TGs, PTs

n[if 424 equals=”Regular Issue”][This article belongs to International Journal of VLSI Circuit Design & Technology(ijvcdt)]

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[/if 424][if 424 equals=”Special Issue”][This article belongs to Special Issue under section in International Journal of VLSI Circuit Design & Technology(ijvcdt)][/if 424][if 424 equals=”Conference”]This article belongs to Conference [/if 424]

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How to cite this article: Vannala Sowmya, P. Sumithabhashini. Design and Implementation of High-Speed Low Power Low Area Hybrid One Bit Full Adder Using CMOS Technology. International Journal of VLSI Circuit Design & Technology. January 12, 2024; 01(02):29-39.

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How to cite this URL: Vannala Sowmya, P. Sumithabhashini. Design and Implementation of High-Speed Low Power Low Area Hybrid One Bit Full Adder Using CMOS Technology. International Journal of VLSI Circuit Design & Technology. January 12, 2024; 01(02):29-39. Available from: https://journals.stmjournals.com/ijvcdt/article=January 12, 2024/view=0

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References

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  1. Frustaci, M. Lanuzza, P. Zicari, S. Perri and P. Corsonello, “Designing High-Speed Adders in Power-Constrained Environments,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56, no. 2, pp. 172-176, Feb. 2009.
  2. Pal, Low Power VLSI Circuits and Systems, New Delhi, India: Springer India, 2015.
  3. Mohanty, “Efficient Fixed-Width Adder-Tree Design,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 2, pp. 292-296, Feb. 2019.
  4. Purohit and M. Margala, “Investigating the impact of logic and circuit implementation for full adder performance,” IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, vol. 20, no. 7, pp. 1327-1331, 2012.
  5. Zimmermann and W. Fichtner, “Low-power logic styles: CMOS versus pass-transistor logic,” IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1079–1090, Jul. 1997.
  6. Yingtao Jiang, A. Al-Sheraidah, Yuke Wang, E. Sha and Jin-Gyun Chung, “A novel multiplexer-based low-power full adder,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 51, no. 7, pp. 345-348, July 2004.
  7. H. E. Weste and D. M. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed. Boston, MA, USA: Addison-Wesley, 2010.
  8. Shams, T.K. Darwish, and M. A. Bayoumi, “Performance analysis of low-power 1-bit CMOS full adder cells,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 1, pp. 20–29, Feb. 2002.
  9. Chang, J. M. Gu, and M. Zhang, “A review of 0.18-μm full adder performances for tree structured arithmetic circuits,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp. 686–695, Jun. 2005.
  10. Alioto, G. Di Cataldo, and G. Palumbo, “Mixed full adder topologies for high-performance low-power arithmetic circuits,” Microelectron. J., vol. 38, no. 1, pp. 130–139, Jan. 2007, Elsevier.
  11. -K. Tung, Y.-C. Hung, S.-H. Shieh, and G.-S. Huang, “A low-power high-speed hybrid CMOS full adder for embedded system,” in Proc. IEEE Conf. Design Diagnostics Electron. Circuits Syst., vol. 13. Apr. 2007, pp. 1–4.
  12. Vesterbacka, “A 14-transistor CMOS full adder with full voltageswing nodes,” in Proc. IEEE Workshop Signal Process. Syst. (SiPS), Taipei, Taiwan, Oct. 1999, pp. 713–722.
  13. T. Bui, Y. Wang, and Y. Jiang, “Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates,” IEEE Transactions on Circuits Systems II: Express Briefs, vol. 49, no. 1, pp. 25–30, Jan. 2002.
  14. Zhang, J. Gu, and C.-H. Chang, “A novel hybrid pass logic with static CMOS output drive full-adder cell,” in Proc. Int. Symp. Circuits Syst., May 2003, pp. 317–320.
  15. Aguirre-Hernandez and M. Linares-Aranda, “CMOS full-adders for energy-efficient arithmetic applications,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 4, pp. 718–721, Apr. 2011.
  16. Hassoune, D. Flandre, I. O’Connor and J. Legat, “ULPFA: A New Efficient Design of a Power-Aware Full Adder,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 8, pp. 2066- 2074, Aug. 2010.
  17. Bhattacharyya, B. Kundu, S. Ghosh, V. Kumar, and A. Dandapat, “Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit,” IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, vol. 23, no. 10, pp. 2001-2008, Oct. 2015.
  18. C. Parameshwara and H. C. Srinivasaiah, “Low-Power Hybrid 1-Bit Full Adder Circuit for Energy Efficient Arithmetic Applications,” Journal of Circuits, Systems and Computers, vol. 26, no. 1, pp. 1-15, 2017.
  19. M Shoba, R Nakkeeran, “GDI based full adders for energy efficient arithmetic applications”, Engineering Science and Technology, an International Journal 19, Elsevier, pp. 485–496, 2016
  20. Pan and A. Naeemi, “A Paradigm Shift in Local Interconnect Technology in the Era of Nanoscale Multigate and Gate-All-Around Devices,” vol. 36, no. 3, pp. 274-276, 2015.

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[if 424 not_equal=””]Regular Issue[else]Published[/if 424] Subscription Review Article

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Volume 01
[if 424 equals=”Regular Issue”]Issue[/if 424][if 424 equals=”Special Issue”]Special Issue[/if 424] [if 424 equals=”Conference”][/if 424] 02
Received December 16, 2023
Accepted January 3, 2024
Published January 12, 2024

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