Rendla Pujitha
R. Ramesh Naik
- M. Tech Student Department of Electronics & Communication Engineering, Holy Trinity Educational Society, Holy Mary Institute of Technology and Science, Kondapur Telangana India
- Assistant Professor Department of Electronics & Communication Engineering, Holy Trinity Educational Society, Holy Mary Institute of Technology and Science, Kondapur Telangana India
Abstract
Our findings reveal a novel kind of circuit capable of performing both XOR and XNOR operations in parallel. Power dissipation and delay are both greatly reduced in the proposed circuits due to their low output capacitance as well as minimal short-circuit power dissipation. We show six new hybrid 1-bit full-adder (FA) circuits that take use of the XOR-XNOR or XOR/XNOR gates’ special full-swing function. Each potential circuit layout has both benefits and drawbacks. The proposed designs are simulated in great detail using HSPICE and Cadence Virtuoso to guarantee their functionality. Simulation findings based on an illustration of a 16-nm CMOS process demonstrate that the proposed designs are faster and more power effective than the initial FA system. To increase the PDP of the circuits, a new method of transistor sizing is developed. The proposed approach employs a particle swarm optimization method based on numerical computing to rapidly and correctly discover the best PDP. The transistor size, input noise immunity, output capacitance, and supply and voltage threshold sensitivity are all taken into account while making circuit recommendations.
Keywords: Full adder circuits, HSPICE, PDP, microprocessors, tablets, CMOS
[This article belongs to International Journal of VLSI Circuit Design & Technology(ijvcdt)]
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References
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| Volume | 01 |
| Issue | 01 |
| Received | July 4, 2023 |
| Accepted | July 24, 2023 |
| Published | November 6, 2023 |