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Journal of VLSI Design Tools and Technology

jovdtt | E-ISSN: 2249-474X | Peer-Reviewed | Hybrid Open Access

About the Journal

Journal of VLSI Design Tools and Technology Journal of VLSI Design Tools & Technology [2249-474X(e)] is a peer-reviewed hybrid open-access journal launched in 2015 focused on the rapid publication of fundamental research papers on all areas of VLSI Design Tools & Technology.

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Journal of VLSI Design Tools & Technology (JOVDTT): 2249-474X(e) is a peer-reviewed hybrid open-access journal launched in 2015 focused on the rapid publication of

Journal Information

Title:
Journal of VLSI Design Tools & Technology
Abbreviation:
JOVDTT
Issues Per Year:
3 Issues (Jan-April,May-August,Sept-Dec)
P-ISSN:
2249-474X
Publisher:
116314
DOI:
Starting Year:
2011
Subject:
Language:
English
Publication Format:
Hybrid Open Access
Copyright Policy:
CC BY-NC-ND
Type:
Peer-reviewed Journal (Refereed Journal)
Address:

Editorial Board

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jovdtt maintains an Editorial Board of practicing researchers from around the world, to ensure manuscripts are handled by editors who are experts in the field of study.

Editor in Chief

Editor

Dr. Brajesh Kumar Kaushik, Professor

Indian Institute of Technology, Roorkee, Uttarakhand, India,

Email :

Latest Articles

A Review on Arduino Based Distance Measurement Device

Distance measurement plays a vital role in modern engineering applications such as robotics, defense systems, automotive safety, industrial automation, and assistive technologies.

Arduino Uno, Ultrasonic Sensor, Radar System, Object Detection, Embedded System, Automation

Architectural Evolution of RISC Processors: From Early Research Prototypes to Modern Industrial Implementations

This paper surveys the architectural evolution of Reduced Instruction Set Computer (RISC) architectures from early research prototypes to modern industrial processors, tracing four decades of design refinement across academic, embedded, server, mobile, and open- hardware ecosystems.

RISC, MIPS, SPARC, ARM, RISC-V, Pipeline Architecture, CPI, Load/Store Architecture.

A Physics-Informed Graph Neural Network Framework for Real- Time Thermal-Aware Fault Prediction and Adaptive Power Optimization in Heterogeneous System-on-Chip Architectures

Heterogeneous System-on-Chip (SoC) architectures are increasingly adopted in edge computing, artificial intelligence, autonomous systems, and high-performance embedded platforms due to their superior computational efficiency and flexibility.

Physics-Informed Graph Neural Network (PI-GNN); Heterogeneous System-on-Chip (SoC); Thermal-Aware Fault Prediction; Adaptive Power Optimization; Electronic Design Automation (EDA); Edge Computing.

Performance and Analysis of 6T, 8T & 10T SRAM Cell in 28nm Technology

Technology scaling into deep sub-micron regimes has significantly increased the design challenges of Static Random Access Memory (SRAM), particularly at the 28 nm technology node.

SRAM, Read/Write Reliability, Leakage Power, 28nm Technology Node, Technology Scaling

Thermally Adaptive Bio-Inspired VLSI Interconnect Model for Next-Generation Embedded Systems

The increasing complexity of next-generation embedded systems has intensified the challenges associated with power dissipation, thermal instability, signal integrity, and interconnect reliability in Very Large- Scale Integration (VLSI) architectures.

VLSI Interconnects; Thermal-Aware Computing; Bio-Inspired Architecture; Embedded Systems; Energy-Efficient Integrated Circuits

Design and Analysis of Low-Power CMOS Inverter Chains for High-Speed Digital Circuits

This report briefly explains the design process, structure, and evaluation of a CMOS inverter designed using a 45 nm technology process with a focus on its propagation delay and power consumption.

CMOS Inverter, Inverter Chains, leakage power analysis, 45nm technology

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