Power Estimation Approach for Artix 7 FPGA using Machine Learning Technique

Open Access

Year : 2021 | Volume : | Issue : 1 | Page : 1-5

    Priya Bamne

  1. Abhishek Singh

  1. Student, Gyan Ganga Institute of Technology and Sciences, Jabalpur, Madhya Pradesh, India
  2. Assistant Professor, Gyan Ganga Institute of Technology and Sciences, Jabalpur, Madhya Pradesh, India


This paper presents the power estimation approach using a suitable machine learning technique. Artix7 FPGA has been chosen as the target FPGA (Field Programmable Gate Arrays) platform for understanding the methodology of power estimation. There are various approaches of power estimation for FPGAs that have been given in the literature viz. probabilistic, statistical, and LUT- based, etc. In the past few years, the demand for hand-handled devices like smartphones, tabs, laptops, and wearables has been enhanced drastically. The preferred core of these hand-handled devices is the ASICs. But due to its low performance, it has been replaced by FPGAs because of its increased speed, short turnaround time, and reduced NRE cost. Now, FPGAs have become an integral part of various DSP and telecommunication systems. Commercial tools like Xpower Analyzer, Xpower Estimator, Vivado, and Quartus II are available for estimating the power of the design implementation as per the power budget requirement. But in order to explore the design space early in the design process, the early power estimation models are used that are available in the literature. However, it has been observed that very few power estimation models are available for the estimation of the power of DSP IP cores. However, this paper discussed a supervised machine learning approach namely curve fitting and regression analysis. The approach formulates the power estimation model based on the resource estimation of the given design from the commercial tool. The major contribution of the thesis is to develop a mathematical model for power estimation of MAC IP core using curve fitting and regression, and validation using available commercial tools i.e. XPower Analyzer.

Keywords: ASIC, FPGA, LUT, SRAM, I/O, power

[This article belongs to Research & Reviews: A Journal of Embedded System & Applications(rrjoesa)]

How to cite this article: Priya Bamne, Abhishek Singh Power Estimation Approach for Artix 7 FPGA using Machine Learning Technique rrjoesa 2021; 9:1-5
How to cite this URL: Priya Bamne, Abhishek Singh Power Estimation Approach for Artix 7 FPGA using Machine Learning Technique rrjoesa 2021 {cited 2021 Apr 02};9:1-5. Available from: https://journals.stmjournals.com/rrjoesa/article=2021/view=90553

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Regular Issue Open Access Article
Volume 9
Issue 1
Received March 17, 2021
Accepted March 25, 2021
Published April 2, 2021