Editor’s Profile

Name: Dr. Rupali Ashok Walunj

Editor : Journal of VLSI Design Tools and Technology

Email:

Affiliation: Matoshri College of Engineering and Research Centre, SPP University, Maharashtra, India 422105

Institutional Profile Link : https://engg.matoshri.edu.in/

About Me

Associate Professor in Electronics & Telecommunication Engineering at Matoshri College of Engineering and Research Centre, SPP University, Maharashtra, India
My expertise are VLSI Design

Recent Publications

  1. Walunj, R.A., Kharate, G.K. Design of DG FinFET based driver circuits for energy efficient sub threshold global interconnects. Analog Integr Circ Sig Process 113, 41–60 (2022). https://doi.org/10.1007/s10470-022-02051-w
  2. Walunj, Rupali and Khule, Shridhar and Pable, S. D. and Kharate, Dr. Gajanan, Performance Comparison of CNFET, CMOS and Hybrid CMOS-CNFET Oscillator Circuits (February 25, 2022). Proceedings of the 3rd International Conference on Contents, Computing & Communication (ICCCC-2022), Available at SSRN: https://ssrn.com/abstract=4043582 or http://dx.doi.org/10.2139/ssrn.4043582
  3. R.A Walunj, G.K. Kharate. Impact of Interconnect Variation on Ultra Low Power Clock System. Journal of Advanced Research in Power Electronics & Power Systems. 2021; Vol. 8 No. 1 & 2 (2021) 5-13. https://adrjournalshouse.com/index.php/power-electronics-power-systems/article/view/1284
  4. Prachi Gupta, Pooja Ahirrao, R.A Walunj. Online Printing Order Management Systems. Journal of Advanced Research in Power Electronics & Power Systems. 2021; Vol. 8 No. 1 & 2 (2021) 5-13. https://adrjournalshouse.com/index.php/power-electronics-power-systems/article/view/1285
  5. Shridhar S. Khule and Rupali A. Walunj. Performance Analysis of 32 NM FINFET and CNFET Oscillator Circuit in Sub Threshold Regime. ICTACT Journal on Microelectronics, October 2022, VOLUME: 08, ISSUE: 03. 1394-1399. https://ictactjournals.in/paper/IJME_Vol_8_Iss_3_Paper_4_1394_1399.pdf