JoSDC

Comparative Study of Drain Current of Symmetric and Asymmetric DG-MOSFET with Simulation in Silvaco TCAD Software

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u00a0Abhishek Saha, Vedatrayee Chakraborty,

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nJanuary 9, 2023 at 9:01 am

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nAbstract

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One of the most attractive and promising devices for the nanoscale devices is the double gate MOSFET. The double gate MOSFET can control the Si channel very efficiently and it chooses a very small width of the Si channel. It controls the Si channel by applying gate contact to either side of the channel. The idea of controlling the S channel in such a way reduces the short channel effects and one can get a higher current as compared with a single gate MOSFET. In this paper, models of both symmetric and asymmetric DG-MOSFET are studied and performance is compared with the performance of single gate strained silicon MOSFET. The model of DG-MOSFET is simulated with Silvaco TCAD device simulator and different characteristic parameters are being studied.

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Volume :u00a0u00a08 | Issue :u00a0u00a01 | Received :u00a0u00a0April 19, 2021 | Accepted :u00a0u00a0May 10, 2021 | Published :u00a0u00a0May 25, 2021n[if 424 equals=”Regular Issue”][This article belongs to Journal of Semiconductor Devices and Circuits(josdc)] [/if 424][if 424 equals=”Special Issue”][This article belongs to Special Issue Comparative Study of Drain Current of Symmetric and Asymmetric DG-MOSFET with Simulation in Silvaco TCAD Software under section in Journal of Semiconductor Devices and Circuits(josdc)] [/if 424]
Keywords Asymmetric DG-MOSFET, device modeling, Silvaco TCAD, strained silicon, symmetric DG-MOSFET

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References

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1. G Moore. Cramming more components onto integrated circuits. Electronics. 1965; 38(8): 114.
2. Jean-Pierre Colinge. FinFETs and Other MultiGate Transistors. Springer; 2008.
3. Ieong M, Wong HSP, Nowak E, Kedzierski J, Jones EC. High performance double-gate device technology challenges and opportunities. Proceedings International Symposium on Quality Electronic Design. San Jose, CA, USA. 2002, March 18–21.
4. Wong HS, Chan K, Taur Y. Self-aligned (top and bottom) double-gate MOSFET with a 25nm thick silicon channel. International Electron Devices Meeting. IEDM Technical Digest. Washington, DC, USA. 1997, Dec. 10.
5. Mehdi Zahid Sadi, Nittaranjan Karmakar, Mohammed Khorshed Alam, et al. Comparative analysis of subthreshold swing models for different double gate MOSFETs. 5th International Conference on Electrical and Computer Engineering ICECE. Dhaka, Bangladesh. 2008, Dec. 20–22.
6. Ankita Wagadre, Shashank Mane. Design & performance analysis of DG-MOSFET for reduction of short channel effect over bulk MOSFET at 20nm. Int. Journal of Engineering Research and Applications. 2014; 4(7): 30–34.
7. Sanjay Chopade, M Shashank Mane. Design of DG-CNFET for reduction of short channel effect over DG MOSFET at 20 nm. 2013 IEEE International Conference of IEEE Region 10 (TENCON 2013). Xi’an, China. 2013, Oct. 22–25.
8. Santosh Kumar Gupta et al. Simulation and analysis of gate engineered triple metal double gate (TM-DG) MOSFET for diminished short channel effects. IJAST. 2012; 38: 15–24.
9. Valco George. Getting started with the Silvaco TCAD software for EE637 and EE734. 2010. [Online] Available at: https://web.archive.org/web/20080828110857/http://www.ece.osu.edu/~ valco/silvaco/index.html.
10. Silvaco. (2019). Silvaco [online] Available at: https://silvaco.com/examples/tcad/section26/example3/index.html.

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[if 424 not_equal=”Regular Issue”] Regular Issue[/if 424] Open Access Article

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Journal of Semiconductor Devices and Circuits

ISSN: 2455-3379

Editors Overview

josdc maintains an Editorial Board of practicing researchers from around the world, to ensure manuscripts are handled by editors who are experts in the field of study.

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    Abhishek Saha, Vedatrayee Chakraborty

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  1. Assistant Professor, Assistant Professor,Dream Institute of Technology, B.P. Poddar Institute of Management and Technology,Kolkata, West Bengal, Kolkata, West Bengal,India, India
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Abstract

nOne of the most attractive and promising devices for the nanoscale devices is the double gate MOSFET. The double gate MOSFET can control the Si channel very efficiently and it chooses a very small width of the Si channel. It controls the Si channel by applying gate contact to either side of the channel. The idea of controlling the S channel in such a way reduces the short channel effects and one can get a higher current as compared with a single gate MOSFET. In this paper, models of both symmetric and asymmetric DG-MOSFET are studied and performance is compared with the performance of single gate strained silicon MOSFET. The model of DG-MOSFET is simulated with Silvaco TCAD device simulator and different characteristic parameters are being studied.n

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Keywords: Asymmetric DG-MOSFET, device modeling, Silvaco TCAD, strained silicon, symmetric DG-MOSFET

n[if 424 equals=”Regular Issue”][This article belongs to Journal of Semiconductor Devices and Circuits(josdc)]

n[/if 424][if 424 equals=”Special Issue”][This article belongs to Special Issue under section in Journal of Semiconductor Devices and Circuits(josdc)] [/if 424]

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References

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1. G Moore. Cramming more components onto integrated circuits. Electronics. 1965; 38(8): 114.
2. Jean-Pierre Colinge. FinFETs and Other MultiGate Transistors. Springer; 2008.
3. Ieong M, Wong HSP, Nowak E, Kedzierski J, Jones EC. High performance double-gate device technology challenges and opportunities. Proceedings International Symposium on Quality Electronic Design. San Jose, CA, USA. 2002, March 18–21.
4. Wong HS, Chan K, Taur Y. Self-aligned (top and bottom) double-gate MOSFET with a 25nm thick silicon channel. International Electron Devices Meeting. IEDM Technical Digest. Washington, DC, USA. 1997, Dec. 10.
5. Mehdi Zahid Sadi, Nittaranjan Karmakar, Mohammed Khorshed Alam, et al. Comparative analysis of subthreshold swing models for different double gate MOSFETs. 5th International Conference on Electrical and Computer Engineering ICECE. Dhaka, Bangladesh. 2008, Dec. 20–22.
6. Ankita Wagadre, Shashank Mane. Design & performance analysis of DG-MOSFET for reduction of short channel effect over bulk MOSFET at 20nm. Int. Journal of Engineering Research and Applications. 2014; 4(7): 30–34.
7. Sanjay Chopade, M Shashank Mane. Design of DG-CNFET for reduction of short channel effect over DG MOSFET at 20 nm. 2013 IEEE International Conference of IEEE Region 10 (TENCON 2013). Xi’an, China. 2013, Oct. 22–25.
8. Santosh Kumar Gupta et al. Simulation and analysis of gate engineered triple metal double gate (TM-DG) MOSFET for diminished short channel effects. IJAST. 2012; 38: 15–24.
9. Valco George. Getting started with the Silvaco TCAD software for EE637 and EE734. 2010. [Online] Available at: https://web.archive.org/web/20080828110857/http://www.ece.osu.edu/~ valco/silvaco/index.html.
10. Silvaco. (2019). Silvaco [online] Available at: https://silvaco.com/examples/tcad/section26/example3/index.html.

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Regular Issue Open Access Article

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Journal of Semiconductor Devices and Circuits

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[if 344 not_equal=””]ISSN: 2455-3379[/if 344]

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Volume 8
Issue 1
Received April 19, 2021
Accepted May 10, 2021
Published May 25, 2021

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JoSDC

Comparative Study of Symmetric and Asymmetric Oxide Double Gate Junction less FET

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u00a0Kunal Kumar,

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nJanuary 9, 2023 at 8:54 am

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we carry out the performance of symmetric oxide (HfO2+HfO2) and asymmetric oxide (SiO2+HfO2) n-type junction less field-effect transistor (JLFET) based on two- dimensional Poisson equation. This study is accomplished by simulating a symmetric and asymmetric double gate JLFET on Sentaurus, Technology Computer Aided Design (TCAD) simulator for Silicon (Si) material at room temperature and varying temperature in between 300-360 k. Based on device simulation we find that the asymmetric oxide shows preferable performance in terms of ON-state current (ION), subthreshold swing(SS), the ION/IOFF ratios (~107 ) and the equivalent oxide thickness (EOT) compared to symmetric devices and also asymmetric oxide technology enhances the performance and reduces the power consumptions.

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Volume :u00a0u00a08 | Issue :u00a0u00a02 | Received :u00a0u00a0October 9, 2021 | Accepted :u00a0u00a0October 21, 2021 | Published :u00a0u00a0October 28, 2021n[if 424 equals=”Regular Issue”][This article belongs to Journal of Semiconductor Devices and Circuits(josdc)] [/if 424][if 424 equals=”Special Issue”][This article belongs to Special Issue Comparative Study of Symmetric and Asymmetric Oxide Double Gate Junction less FET under section in Journal of Semiconductor Devices and Circuits(josdc)] [/if 424]
Keywords EOT, Symmetric, TCAD, (SS), (ION), (EOT).

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1. C. Lee et al., “High-Temperature Performance of Silicon Junctionless MOSFETs,” in IEEE Transactions on Electron Devices, vol. 57, no. 3, pp. 620-625, March 2010, doi:10.1109/TED.2009.2039093.
2. X. Li, W. Han, L. Ma, H. Wang, Y. Zhang and F. Yang, “Low-Temperature Quantum Transport Characteristics in Single n-Channel Junctionless Nanowire Transistors,” in IEEE Electron Device Letters, vol. 34, no. 5, pp. 581-583, May 2013, doi: 10.1109/LED.2013.2250898.
3. K. Kumar, Y. Hsieh, J. Liao, K. Kao and Y. Wang, “Significance of Multivalley and Nonparabolic Band Structure for GeSn TFET Simulation,” in IEEE Transactions on Electron Devices, vol. 65, no. 10, pp. 4709-4715, Oct. 2018, doi: 10.1109/TED.2018.2864544.
4. S. Sahay and M. J. Kumar, “Realizing Efficient Volume Depletion in SOI Junctionless FETs,” in IEEE Journal of the Electron Devices Society, vol. 4, no. 3, pp. 110-115, May 2016, doi:10.1109/JEDS.2016.2532965.
5. J. Colinge, “Junctionless transistors,” 2012 IEEE International Meeting for Future of Electron Devices, Kansai, 2012, pp. 1-2, doi: 10.1109/IMFEDK.2012.6218561.
6. M. Berthomé, S. Barraud, A. Ionescu and T. Ernst, “Physically-based, multi-architecture, analytical model for junctionless transistors,” Ulis 2011 Ultimate Integration on Silicon, 2011, pp.1-4, doi: 10.1109/ULIS.2011.5757988.
7. Sahu, S.R.; Agrawal, R.S.; Balwani, S.M. Review of Junctionless transistor using CMOS technology and MOSFETs. Int. J. Comput. Appl. 2012, 2012, 8–11
8. J.P. Colinge, A. Kranti, R. Yan, C.W. Lee, I. Ferain, R. Yu, N. Dehdashti Akhavan, P. Razavi, Junctionless Nanowire Transistor (JNT): Properties and design guidelines, Solid-State Electronics, Volumes 65–66, 2011, Pages 33-37, ISSN 0038-1101.
9. Ang, J.; Wan, Q.; Zhang, Q. Transparent junctionless electric-double-layer transistors gated by a reinforced chitosan-based biopolymer electrolyte. IEEE Trans. Electron. Devices 2013, 60, 1951–1957.
10. R. Rios et al., “Comparison of Junctionless and Conventional Trigate Transistors With $L_{g}$Down to 26 nm,” in IEEE Electron Device Letters, vol. 32, no. 9, pp. 1170-1172, Sept. 2011,doi:10.1109/LED.2011.2158978.
11. Robertson, John. “High dielectric constant oxides.” The European Physical Journal-Applied Physics 28.3 (2004): 265-291.
12. R. K. Baruah and R. P. Paily, “High-temperature effects on device performance of a junctionless transistor,” 2012Int. Conf. Emerg. Electron. ICEE 2012, 2012.
13. S. Sahay and M. J. Kumar, “Controlling L-BTBT and Volume Depletion in Nanowire JLFETs Using Core–Shell Architecture,” in IEEE Transactions on Electron Devices, vol. 63, no. 9, pp.3790-3794, Sept. 2016, doi: 10.1109/TED.2016.2591588.
14. Ming-Hung Han, Hung-Bin Chen, Shiang-Shiou Yen, Chi-Shen Shao, and Chun-Yen Chang ,”Temperature-dependent characteristics of junctionless bulk transistor”, Applied Physics Letters 103, 133503 (2013) https://doi.org/10.1063/1.4821747.
15. Lü, Wei-Feng, and Liang Dai. “Impact of work-function variation on analog figures-of-merits for high-k/metal-gate junctionless FinFET and gate-all-around nanowire MOSFET.” Microelectronics Journal 84 (2019): 54-58.

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[if 424 not_equal=”Regular Issue”] Regular Issue[/if 424] Open Access Article

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Journal of Semiconductor Devices and Circuits

ISSN: 2455-3379

Editors Overview

josdc maintains an Editorial Board of practicing researchers from around the world, to ensure manuscripts are handled by editors who are experts in the field of study.

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    By  [foreach 286]n

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    Kunal Kumar

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  1. Research Associate,National Cheng Kung University Tainan,,Taiwan
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Abstract

nwe carry out the performance of symmetric oxide (HfO2+HfO2) and asymmetric oxide (SiO2+HfO2) n-type junction less field-effect transistor (JLFET) based on two- dimensional Poisson equation. This study is accomplished by simulating a symmetric and asymmetric double gate JLFET on Sentaurus, Technology Computer Aided Design (TCAD) simulator for Silicon (Si) material at room temperature and varying temperature in between 300-360 k. Based on device simulation we find that the asymmetric oxide shows preferable performance in terms of ON-state current (ION), subthreshold swing(SS), the ION/IOFF ratios (~107 ) and the equivalent oxide thickness (EOT) compared to symmetric devices and also asymmetric oxide technology enhances the performance and reduces the power consumptions.n

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Keywords: EOT, Symmetric, TCAD, (SS), (ION), (EOT).

n[if 424 equals=”Regular Issue”][This article belongs to Journal of Semiconductor Devices and Circuits(josdc)]

n[/if 424][if 424 equals=”Special Issue”][This article belongs to Special Issue under section in Journal of Semiconductor Devices and Circuits(josdc)] [/if 424]

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Browse Figures

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References

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1. C. Lee et al., “High-Temperature Performance of Silicon Junctionless MOSFETs,” in IEEE Transactions on Electron Devices, vol. 57, no. 3, pp. 620-625, March 2010, doi:10.1109/TED.2009.2039093.
2. X. Li, W. Han, L. Ma, H. Wang, Y. Zhang and F. Yang, “Low-Temperature Quantum Transport Characteristics in Single n-Channel Junctionless Nanowire Transistors,” in IEEE Electron Device Letters, vol. 34, no. 5, pp. 581-583, May 2013, doi: 10.1109/LED.2013.2250898.
3. K. Kumar, Y. Hsieh, J. Liao, K. Kao and Y. Wang, “Significance of Multivalley and Nonparabolic Band Structure for GeSn TFET Simulation,” in IEEE Transactions on Electron Devices, vol. 65, no. 10, pp. 4709-4715, Oct. 2018, doi: 10.1109/TED.2018.2864544.
4. S. Sahay and M. J. Kumar, “Realizing Efficient Volume Depletion in SOI Junctionless FETs,” in IEEE Journal of the Electron Devices Society, vol. 4, no. 3, pp. 110-115, May 2016, doi:10.1109/JEDS.2016.2532965.
5. J. Colinge, “Junctionless transistors,” 2012 IEEE International Meeting for Future of Electron Devices, Kansai, 2012, pp. 1-2, doi: 10.1109/IMFEDK.2012.6218561.
6. M. Berthomé, S. Barraud, A. Ionescu and T. Ernst, “Physically-based, multi-architecture, analytical model for junctionless transistors,” Ulis 2011 Ultimate Integration on Silicon, 2011, pp.1-4, doi: 10.1109/ULIS.2011.5757988.
7. Sahu, S.R.; Agrawal, R.S.; Balwani, S.M. Review of Junctionless transistor using CMOS technology and MOSFETs. Int. J. Comput. Appl. 2012, 2012, 8–11
8. J.P. Colinge, A. Kranti, R. Yan, C.W. Lee, I. Ferain, R. Yu, N. Dehdashti Akhavan, P. Razavi, Junctionless Nanowire Transistor (JNT): Properties and design guidelines, Solid-State Electronics, Volumes 65–66, 2011, Pages 33-37, ISSN 0038-1101.
9. Ang, J.; Wan, Q.; Zhang, Q. Transparent junctionless electric-double-layer transistors gated by a reinforced chitosan-based biopolymer electrolyte. IEEE Trans. Electron. Devices 2013, 60, 1951–1957.
10. R. Rios et al., “Comparison of Junctionless and Conventional Trigate Transistors With $L_{g}$Down to 26 nm,” in IEEE Electron Device Letters, vol. 32, no. 9, pp. 1170-1172, Sept. 2011,doi:10.1109/LED.2011.2158978.
11. Robertson, John. “High dielectric constant oxides.” The European Physical Journal-Applied Physics 28.3 (2004): 265-291.
12. R. K. Baruah and R. P. Paily, “High-temperature effects on device performance of a junctionless transistor,” 2012Int. Conf. Emerg. Electron. ICEE 2012, 2012.
13. S. Sahay and M. J. Kumar, “Controlling L-BTBT and Volume Depletion in Nanowire JLFETs Using Core–Shell Architecture,” in IEEE Transactions on Electron Devices, vol. 63, no. 9, pp.3790-3794, Sept. 2016, doi: 10.1109/TED.2016.2591588.
14. Ming-Hung Han, Hung-Bin Chen, Shiang-Shiou Yen, Chi-Shen Shao, and Chun-Yen Chang ,”Temperature-dependent characteristics of junctionless bulk transistor”, Applied Physics Letters 103, 133503 (2013) https://doi.org/10.1063/1.4821747.
15. Lü, Wei-Feng, and Liang Dai. “Impact of work-function variation on analog figures-of-merits for high-k/metal-gate junctionless FinFET and gate-all-around nanowire MOSFET.” Microelectronics Journal 84 (2019): 54-58.

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Volume 8
Issue 2
Received October 9, 2021
Accepted October 21, 2021
Published October 28, 2021

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