E-ISSN: 2249-474X | P-ISSN: 2321-6492 | Peer-Reviewed Journal (Refereed Journal) | Hybrid Open Access
Journal of VLSI Design Tools and Technology Journal of VLSI Design Tools & Technology [2249-474X(e)]Â is a peer-reviewed hybrid open-access journal launched in 2015 focused on the rapid publication of fundamental research papers on all areas of VLSI Design Tools & Technology.
jovdtt maintains an Editorial Board of practicing researchers from around the world, to ensure manuscripts are handled by editors who are experts in the field of study.
Dr. Brajesh Kumar Kaushik, Professor
Indian Institute of Technology, Roorkee, Uttarakhand, India,
Email :
Institutional Profile Link: http://ece.iitr.ac.in/brajesh_kumar_kaushik
Technology scaling into deep sub-micron regimes has significantly increased the design challenges of Static Random Access Memory (SRAM), particularly at the 28 nm technology node.
The increasing complexity of next-generation embedded systems has intensified the challenges associated with power dissipation, thermal instability, signal integrity, and interconnect reliability in Very Large- Scale Integration (VLSI) architectures.
This report briefly explains the design process, structure, and evaluation of a CMOS inverter designed using a 45 nm technology process with a focus on its propagation delay and power consumption.
Multiply and Accumulate (MAC) units are essential parts of digital systems, particularly in embedded systems, digital signal processing (DSP), and image processing.
Very Large Scale Integration (VLSI) design is still one of the most active and important areas of the semiconductor industry.
Two-wheeled self-balancing robots (TWSBR) are a popular application of embedded control and robotics because they operate on the inverted pendulum concept, which is naturally unstable.
