Total Articles : 5

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26-May-2026
Ahead of Print  Subscription Review Article Published on :- 26-May-2026

An Overview on VLSI based Hardware Security in IoT Node

By
Kazi Kutubuddin Sayyad Liyakat, Heena Shaikh, Dr. Kosgiker G M,

Abstract: In the coming era, security will not be a feature we add to an IoT device; it will be a property inherent to its transistor-level design. By encoding security into the VLSI architecture, we move away from the fragile “software-only” paradigm and


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15-May-2026
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A Comprehensive Review of CMOS Analog Circuit Design Techniques for Low-Power VLSI Systems

By
Heena T Shaikh, Kazi Kutubuddin Sayyad Liyakat,

Abstract: CMOS analog circuit design plays a significant role in the development of modern low-power Very Large-Scale Integration (VLSI) systems used in wireless communication, biomedical devices, portable electronics, embedded systems, and Internet of Things


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15-May-2026
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Machine Learning Assisted Timing Violation Prediction in Sub-7nm VLSI Physical Design

By
Rosalin Pradhan, Bibhu Prasad Ganthia,

Abstract: The continuous scaling of semiconductor technology into the sub-7nm regime has introduced significant challenges in timing closure due to process variability, interconnect delay, power density, and manufacturing uncertainties. Conventional static


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15-May-2026
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Spintronic Logic Device Modeling and Energy Optimization for Beyond-CMOS Computing Systems

By
Bibhu Prasad Ganthia, Rosalin Pradhan,

Abstract: The continuous scaling limitations of conventional CMOS technology have accelerated the exploration of alternative computing paradigms for next-generation low-power and high-performance systems. Spintronic logic devices have emerged as a promising


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05-May-2026
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64 Bit ALU DESIGN USING VEDIC MATHEMATHICS

By
Sirigineedi Mounisha, Uppalapati Joshna Venkata Srujana, Vemula Rajesh, Velugubanti Lakshman, Yepuganti Manikanta, I.Rama Satya.Nageswara Rao, Saran Kumar,

Abstract: High-speed arithmetic operations are crucial for better performance in contemporary digital systems. Particularly for high bit-width operations, conventional arithmetic logic units (ALUs) frequently experience increased latency and complexity. This