Implementation of STATIC-RANDOM-ACCESS-MEMORY-Based In-Memory Computing-architecture for improving Energy Efficiency

Year : 2025 | Volume : 15 | Issue : 01 | Page : 25 35
    By

    Kiran Sharma,

  • Jitendra Ahir,

  • Laxmi Singh,

  1. Ph.D. Scholar, Department of Electronics and Communication Engineering, Rabindranath Tagore University, Bhopal, Madhya Pradesh, India
  2. Assistant Professor, Department of Electronics and Communication Engineering, Rabindranath Tagore University, Bhopal, Madhya Pradesh, India
  3. Professor, Department of Electronics and Communication Engineering, Rabindranath Tagore University, Bhopal, Madhya Pradesh, India

Abstract

The in-memory-computing architecture the improvement of big data and high-performance computing. In memory-computing (IMC) as reduces the latency and power consumption of data processing. Proposed research paper static random-access memory-based IMC architecture. By completing internal write-back, NMOS transistors increase computational efficiency and eliminate the need to read the computational output right away. A 128×128 STATIC-RANDOM-ACCESS-MEMORY-IMC macro chip is designed using the 78-nm technology. The energy efficiency of 55.3TOPS/W with supply voltage 1.2V and a throughput of 224.1 GOPS/mm2. A neural network using the suggested STATIC-RANDOM-ACCESS-MEMORY IMC architecture achieves 95% accuracy with the Mixed Signal. In-memory computing (IMC) architecture based on static random-access memory (SRAM) presents a viable way to address the rising energy requirements of data-centric applications in contemporary computer systems. SRAM-based IMC reduces data travel by integrating processing into memory arrays, greatly enhancing computational performance and energy efficiency. The implementation of SRAM-based IMC architecture is examined in this paper, with particular attention paid to its approach, advantages, and difficulties. We describe the design ideas, energy-efficient features, and machine learning (ML) and artificial intelligence (AI) applications of architecture. We show through a comparative analysis that SRAM-based IMC performs better in terms of latency and energy economy than conventional von Neumann architecture, opening the door for high-performance and environmentally friendly computing systems.

Keywords: In-memory-computing (IMC), Static-Random-Access-Memory, Row by Row ADC, NMOS, IMC, ML, AI, XNOR gates

[This article belongs to Journal of VLSI Design Tools and Technology ]

How to cite this article:
Kiran Sharma, Jitendra Ahir, Laxmi Singh. Implementation of STATIC-RANDOM-ACCESS-MEMORY-Based In-Memory Computing-architecture for improving Energy Efficiency. Journal of VLSI Design Tools and Technology. 2025; 15(01):25-35.
How to cite this URL:
Kiran Sharma, Jitendra Ahir, Laxmi Singh. Implementation of STATIC-RANDOM-ACCESS-MEMORY-Based In-Memory Computing-architecture for improving Energy Efficiency. Journal of VLSI Design Tools and Technology. 2025; 15(01):25-35. Available from: https://journals.stmjournals.com/jovdtt/article=2025/view=195632


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Regular Issue Subscription Original Research
Volume 15
Issue 01
Received 21/01/2025
Accepted 25/01/2025
Published 28/01/2025
Publication Time 7 Days
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