Sandeep N. Uttarkar,
K. B. Ramesh,
- Student,, R.V. College of Engineering ,Banglore,, Karnataka, India.
- Associate professor, R.V. College of Engineering ,Banglore,, Karnataka, India
Abstract
In the new age world, where the modern technology has vast applications in various fields of Engineering, Medicine and others. Digital Electronics processing and systems play a vital role in analysis and computation of data representation. Electronics systems have gradually become faster and smaller scaled. The primary structural element of any modern ALU-based processor is an adder. Addition is a well-known extremely basic function that is employed in nearly all computing processes. The performance of the adder circuit will therefore greatly affect the performance of the CPU. In terms of frequency, general adders like half adders, full adders, ripple carry adders, carry skip adders, and carry look-ahead adders don’t meet the demands of high-performance processors. To fulfil the required specifications, we suggested in this work a high-frequency 16-bit full adder architecture. This architecture was simulated using Verilog on the Xilinx ISE 14.7 tool, and it was then built on the FPGA families.
Keywords: Half Adder (HA), Full Adder (FA), Carry Select Adder (CSA), Carry Look Ahead Adder (CLA), Input Output Blocks (IOB), Configurable logic blocks (CLB), Field Programmable Gate Array (FPGA).
[This article belongs to Journal of VLSI Design Tools and Technology (jovdtt)]
Sandeep N. Uttarkar, K. B. Ramesh. Design and Implementation of Low latency 16-bit Full Adder. Journal of VLSI Design Tools and Technology. 2024; 14(03):21-30.
Sandeep N. Uttarkar, K. B. Ramesh. Design and Implementation of Low latency 16-bit Full Adder. Journal of VLSI Design Tools and Technology. 2024; 14(03):21-30. Available from: https://journals.stmjournals.com/jovdtt/article=2024/view=176363
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| Volume | 14 |
| Issue | 03 |
| Received | 13/08/2024 |
| Accepted | 21/08/2024 |
| Published | 30/09/2024 |