Hetav Desai Desai,
Zaid Gugarman,
Pallavi Darji,
Mitesh Limbachia,
- UG graduate,, Dharmsinh Desai Institute of Technology,, Nadiad,, India
- UG graduate,, Dharmsinh Desai Institute of Technology,, Nadiad,, India
- Associate Professor,, Dharmsinh Desai Institute of Technology,, Nadiad,, India
- Assistant Professor, Dharmsinh Desai Institute of Technology,, Nadiad,, India
Abstract
At lower nodes of CMOS technology, noise within a chip increase due to a drastic increment in interconnects within a given area. To improve the noise immunity of a chip, a Schmitt trigger circuit is used as a buffer instead of a simple CMOS inverter at various intervals along the metal interconnect. The use of a Schmitt trigger circuit not only makes the chip noise immune but also increases the speed of operation. Different typologies of Schmitt trigger circuits, such as 4T, 6T, and 6T with body bias, are studied, implemented, and analyzed based on speed, area, power, and hysteresis. Since there is a trade-off between these parameters, the Power Delay Product (PDP) is determined, and the best one will be chosen as per the requirement. The Schmitt trigger circuit is also used in IO pads surrounding the chip and in a bidirectional bus as a tristate buffer in a communication system. The 4T Schmitt trigger is found82% lower Power-Delay Product (PDP) compared to the conventional 6T Schmitt trigger circuit. Modern electronics have become more susceptible to noise due to the shrinking of components and the growing complexity of integrated circuits. This can cause irregular behaviour and a deterioration in signal integrity. One common remedy for noise-related problems is the Schmitt trigger circuit. By supplying hysteresis, it guarantees steady signal processing and eliminates undesired noise in digital systems. Schmitt trigger circuit design, functionality, and performance are examined in this article, with a focus on their use in the production of noise-free semiconductors.
Keywords: CMOS, Schmitt Trigger, Power, Hysteresis, Propagation Delay, Noise, Buffer
[This article belongs to Journal of VLSI Design Tools and Technology (jovdtt)]
Hetav Desai Desai, Zaid Gugarman, Pallavi Darji, Mitesh Limbachia. Performance Analysis of Schmitt Trigger Circuit for Noise-Free Chips. Journal of VLSI Design Tools and Technology. 2024; 14(03):11-20.
Hetav Desai Desai, Zaid Gugarman, Pallavi Darji, Mitesh Limbachia. Performance Analysis of Schmitt Trigger Circuit for Noise-Free Chips. Journal of VLSI Design Tools and Technology. 2024; 14(03):11-20. Available from: https://journals.stmjournals.com/jovdtt/article=2024/view=176347
References
- V.L Pavan Kumar, V.S.V. Prabhakar, Madala Durga Bhavani, Kowtharapu Geetha, Maddukuri Venkatesh, K Hari Kishore, “Design and Analysis of CMOS Schmitt Trigger”, International Journal of Innovative Technology and Exploring Engineering (IJITEE). Volume-8, Issue-7S, May 2019
- Khanna and R. Gupta, “Design, Implementation and Analysis of Different Models of CMOS Schmitt Trigger,” 2018 International Conference on Intelligent Circuits and Systems (ICICS), Phagwara, India, 2018, pp. 63-68, doi: 10.1109/ICICS.2018.00025.
- Kumawat, D. S. Ajnar and P. K. Jain, “Design and Analysis of Noise Immune High Speed and Leakage-Tolerant Schmitt Trigger using 180nm CMOS Technology,” 2021 IEEE Madras Section Conference (MASCON), Chennai, India, 2021, pp. 1-5, doi: 10.1109/MASCON51689.2021.9563581.
- Goka KR, Saini LM. Comparative Analysis of CMOS Schmitt Triggers. In2023 3rd International Conference on Mobile Networks and Wireless Communications (ICMNWC) 2023 Dec 4 (pp. 1-5). IEEE.
- A. Pasini Melek, A. L. da Silva, M. C. Schneider and C. Galup-Montoro, “Analysis and Design of the Classical CMOS Schmitt Trigger in Subthreshold Operation,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 4, pp. 869-878, April 2017, doi: 10.1109/TCSI.2016.2631726.
- Mohamed R. Elmezayen, Wei Hu, Amr M. Maghraby, Islam T. Abougindia and Suat U. Ay, “ACCURATE ANALYSIS AND DESIGN OF INTEGRATED SINGLE INPUT SCHMITT TRIGGER CIRCUITS,’”/. Low Power Electron. Appl. 2020, 10(3), 21; https://doi.org/10.3390/jlpea10030021
- S. Joseph, R. Shukla and V. Niranjan, “Performance evaluation of low voltage Schmitt triggers using variable Threshold techniques,” 2015 4th International Conference on Reliability, Infocom Technologies and Optimization (ICRITO) (Trends and Future Directions), Noida, India, 2015, pp. 1-5, doi: 10.1109/ICRITO.2015.7359347.
- Saini S, Veeramachaneni S, Kumar AM, Srinivas MB. Schmitt trigger as an alternative to buffer insertion for delay and power reduction in VLSI interconnects. InTENCON 2009-2009 IEEE Region 10 Conference 2009 Jan 23 (pp. 1-5). IEEE.
- Niranjan V, Gupta M. An Analytical model of the Bulk-DTMOS transistor. Journal of Electron Devices. 2010;8(2010):329-38.
- Kulkarni JP, Kim K, Roy K. A 160-mV robust Schmitt trigger based subthreshold SRAM. IEEE Journal of Solid-State Circuits. 2007 Sep 24;42(10):2303-13.
| Volume | 14 |
| Issue | 03 |
| Received | 21/08/2024 |
| Accepted | 27/08/2024 |
| Published | 30/09/2024 |