Ayushi Vinodia,
Kanchan Cecil,
- Student, Jabalpur Engineering College, Madhya Pradesh, India
- Professor, Jabalpur Engineering College, Madhya Pradesh, India
Abstract
This paper presents a novel HS-14T design aimed at significantly improving read and write delays compared to conventional 6T and other memory cells RHRD-12T, SEUH-12T, and NHRC-14T. As technology scales, the demand for faster and more stable memory cells becomes increasingly critical. Our proposed HS-14T incorporates additional transistors to enhance stability and reduce access times, resulting in notable performance gains. Comprehensive simulations reveal that the HS-14T SRAM cell substantially reduces read and write delays, outperforming traditional 6T, RHRD-12T, SEUH-12T, and NHRC-14T SRAM cells. Specifically, the HS-14T demonstrates an impressive 80% reduction in read delay compared to NHRC-14T, an 88% reduction compared to RHRD-12T, and an 89% reduction compared to SEUH-14. In terms of write delay, the HS-14T shows a 66% reduction compared to NHRC-14T, a 98.75% reduction compared to RHRD-12T, and a 25% reduction compared to SEUH-14. Additionally, the HS-14T exhibits an 18% decrease in leakage current compared to RHRD-12T and a 1.63% decrease compared to SUEH-12T, though it shows a 55% increase compared to NHRC-14T. The software used for simulations is Symica DE, and the technology node is 45 nm. This study highlights the HS-14T SRAM’s potential for significantly enhanced performance and productivity in various computing systems, making it a compelling choice for applications where rapid data access and energy efficiency are paramount.
Keywords: SRAM cell, read delay, write delay leakage current, Symica DE, minicomputers, cache memory
[This article belongs to Journal of VLSI Design Tools and Technology(jovdtt)]
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Journal of VLSI Design Tools and Technology
Volume | 14 |
Issue | 02 |
Received | July 5, 2024 |
Accepted | July 24, 2024 |
Published | August 7, 2024 |