- Student, SRES’s Sanjivani College of Engineering, Kopargaon, Maharashtra, India
- Professor, SRES’s Sanjivani College of Engineering, Kopargaon, Maharashtra, India
Continued developments in microelectronics technology have led to a myriad of new compute- intensive applications at the micro-edge, such as artificial intelligence and signal and image processing. Multiplication is a crucial arithmetic process in such applications. However, large logic complexities typically seen in traditional multipliers generate combinatorial blocks with long chains of cascaded carry addition. As such, energy efficiency has remained a primary design challenge for these applications, when powered by batteries or emerging energy harvesters. Hardware multipliers are an essential component of signal processes and related algorithms embedded within numerous multimedia and communication systems. In Arithmetic Logic Unit (ALU) one-bit full adder is one of the most repeatedly used digital circuit component which is most integral functional unit of all computational circuit. In this paper CMOS CNFET, Memristor based full adder and Multiplexer circuits are implemented at 45nm, 180nm and 32nm technology and performance parameters such as Power Delay Product (PDP), Propagation Delay and Power Consumption are compared using Cadence Virtuoso, HSPICE and LTSPICE simulator software.
Keywords: CMOS, CNFET, Memristor Full Adder, Multiplexer, PDP
[This article belongs to Journal of VLSI Design Tools & Technology(jovdtt)]
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|Received||July 7, 2022|
|Accepted||July 15, 2022|
|Published||July 29, 2022|