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u00a0Priya Bamne, Abhishek Singh,
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nJanuary 9, 2023 at 6:22 am
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nAbstract
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This paper presents the power estimation approach using a suitable machine learning technique. Artix7 FPGA has been chosen as the target FPGA (Field Programmable Gate Arrays) platform for understanding the methodology of power estimation. There are various approaches of power estimation for FPGAs that have been given in the literature viz. probabilistic, statistical, and LUT- based, etc. In the past few years, the demand for hand-handled devices like smartphones, tabs, laptops, and wearables has been enhanced drastically. The preferred core of these hand-handled devices is the ASICs. But due to its low performance, it has been replaced by FPGAs because of its increased speed, short turnaround time, and reduced NRE cost. Now, FPGAs have become an integral part of various DSP and telecommunication systems. Commercial tools like Xpower Analyzer, Xpower Estimator, Vivado, and Quartus II are available for estimating the power of the design implementation as per the power budget requirement. But in order to explore the design space early in the design process, the early power estimation models are used that are available in the literature. However, it has been observed that very few power estimation models are available for the estimation of the power of DSP IP cores. However, this paper discussed a supervised machine learning approach namely curve fitting and regression analysis. The approach formulates the power estimation model based on the resource estimation of the given design from the commercial tool. The major contribution of the thesis is to develop a mathematical model for power estimation of MAC IP core using curve fitting and regression, and validation using available commercial tools i.e. XPower Analyzer.
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Keywords ASIC, FPGA, LUT, SRAM, I/O, power
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References
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1. A Abdollahi, F Fallah, M Pedram. Runtime mechanisms for leakage current reduction in CMOS VLSI circuits. Proceedings of the International Symposium on Low Power Electronics and Design, 2002. Monterey, USA. Aug 12–14.
2. KKW Poon, SJE Wilton, A Yan. A detailed power model for field-programmable gate arrays. ACM Transaction on Design Automation of Electronic Systems. 2005; 10(2): 279–302.
3. SF Johann, MT Moreira, LS Heck, et al. A processor for IoT applications: an assessment of design space and trade-offs. Microprocessor and Microsystems. 2016; 42: 156–164.
4. AM Ortiz, D Hussein, S Park, et al. The cluster between internet of things and social networks: review and research challenges. IEEE Internet of Things Journal. 2014; 1(3): 206–215.
5. R Nane, VM Sima, C Pilato, J Choi, B Fort, et al. A survey and evaluation of FPGA high-level synthesis tools. IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems.2015; 35(10): 1591–1604.
6. D Navarro, Ó Lucı, LA Barragán, et al. High-level synthesis for accelerating the FPGA implementation of computationally demanding control algorithms for power converters. IEEE Transaction on Industrial Informatics. 2013; 9(3): 1371–1379.
7. A Canis et al. LegUp: High-level synthesis for FPGA-based processor/accelerator systems. Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays. Monterey, US. 2011, Feb 27–Mar 1.
8. JH Anderson. Power optimization and prediction techniques for FPGAs [Ph.D. thesis]. Toronto, Canada: Department of Electrical and Computer Engineering University of Toronto; 2005. p. 188.
9. C Maxfield. The Design Warrior’s Guide to FPGAs: Devices, Tools and Flows. Amsterdam: Elsevier; 2004.
10. LJ Goeders, M Wainberg, A Somerville, et al. VTR 7.0: Next generation architecture and CAD system for FPGAs. ACM Transactions on Reconfigurable Technology and Systems. 2014; 7(2):1–30.
11. T Kumar, B Pandey, SHA Musavi, et al. CTHS based energy efficient thermal aware image ALU design on FPGA. Wireless Personal Communications. 2015; 83(1): 671–696. 12. Xilinx. Vivado Design Suite Designing with IP Tutorial User Guide. April 5, 2017.
13. NCK Choy, SJE Wilton. Activity based power estimation and characterization of DSP and multiplier blocks in FPGAs. International Conference on Field Programmable Technology. Bangkok, Thailand. 2006, Dec. 13–15.
14. D Elleouet, N Julien, D Houzet, JG Cousin, E Martin. Power consumption characterization and modeling of embedded memories in XILINX VIRTEX 400E FPGA. Proceedings of the Euromicro Symposium on Digital System Design. Rennes, France. 2004, 31 Aug–3 Sep.
15. A Amira, S Chandrasekaran. Power modeling and efficient FPGA implementation of FHT for signal processing. IEEE Transactions on VLSI Systems. 2007; 15(3): 286–295.
16. D Elleouet, N Julien, D Houzet. A high level SoC power estimation based on IP modeling. 20th Proceedings of IEEE International Parallel & Distributed Processing Symposium. Rhodes, Greece. 2006, April 25–29.
17. S Chandrasekaran, A Amira. A new behavioural power modelling approach for FPGA based custom cores. NASA/ESA Conference on Adaptive Hardware and Systems. Edinburgh, UK. 2007, Aug. 5–8.
18. Hassan N Abdallah. A Complete Power Estimation Methodology for DSP Blocks in FPGAs.International Symposium on Quality Electronic Design. Santa Clara, USA. 2012, March 19–21.
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Journal Menu
Editors Overview
rrjoesa maintains an Editorial Board of practicing researchers from around the world, to ensure manuscripts are handled by editors who are experts in the field of study.
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- By [foreach 286]n
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Priya Bamne, Abhishek Singh
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- Student, Assistant Professor,Gyan Ganga Institute of Technology and Sciences, Gyan Ganga Institute of Technology and Sciences,Jabalpur, Madhya Pradesh, Jabalpur, Madhya Pradesh,India, India
n[/if 1175][/foreach]
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Abstract
nThis paper presents the power estimation approach using a suitable machine learning technique. Artix7 FPGA has been chosen as the target FPGA (Field Programmable Gate Arrays) platform for understanding the methodology of power estimation. There are various approaches of power estimation for FPGAs that have been given in the literature viz. probabilistic, statistical, and LUT- based, etc. In the past few years, the demand for hand-handled devices like smartphones, tabs, laptops, and wearables has been enhanced drastically. The preferred core of these hand-handled devices is the ASICs. But due to its low performance, it has been replaced by FPGAs because of its increased speed, short turnaround time, and reduced NRE cost. Now, FPGAs have become an integral part of various DSP and telecommunication systems. Commercial tools like Xpower Analyzer, Xpower Estimator, Vivado, and Quartus II are available for estimating the power of the design implementation as per the power budget requirement. But in order to explore the design space early in the design process, the early power estimation models are used that are available in the literature. However, it has been observed that very few power estimation models are available for the estimation of the power of DSP IP cores. However, this paper discussed a supervised machine learning approach namely curve fitting and regression analysis. The approach formulates the power estimation model based on the resource estimation of the given design from the commercial tool. The major contribution of the thesis is to develop a mathematical model for power estimation of MAC IP core using curve fitting and regression, and validation using available commercial tools i.e. XPower Analyzer.n
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Keywords: ASIC, FPGA, LUT, SRAM, I/O, power
n[if 424 equals=”Regular Issue”][This article belongs to Research & Reviews: A Journal of Embedded System & Applications(rrjoesa)]
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Full Text
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Browse Figures
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References
n[if 1104 equals=””]
1. A Abdollahi, F Fallah, M Pedram. Runtime mechanisms for leakage current reduction in CMOS VLSI circuits. Proceedings of the International Symposium on Low Power Electronics and Design, 2002. Monterey, USA. Aug 12–14.
2. KKW Poon, SJE Wilton, A Yan. A detailed power model for field-programmable gate arrays. ACM Transaction on Design Automation of Electronic Systems. 2005; 10(2): 279–302.
3. SF Johann, MT Moreira, LS Heck, et al. A processor for IoT applications: an assessment of design space and trade-offs. Microprocessor and Microsystems. 2016; 42: 156–164.
4. AM Ortiz, D Hussein, S Park, et al. The cluster between internet of things and social networks: review and research challenges. IEEE Internet of Things Journal. 2014; 1(3): 206–215.
5. R Nane, VM Sima, C Pilato, J Choi, B Fort, et al. A survey and evaluation of FPGA high-level synthesis tools. IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems.2015; 35(10): 1591–1604.
6. D Navarro, Ó Lucı, LA Barragán, et al. High-level synthesis for accelerating the FPGA implementation of computationally demanding control algorithms for power converters. IEEE Transaction on Industrial Informatics. 2013; 9(3): 1371–1379.
7. A Canis et al. LegUp: High-level synthesis for FPGA-based processor/accelerator systems. Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays. Monterey, US. 2011, Feb 27–Mar 1.
8. JH Anderson. Power optimization and prediction techniques for FPGAs [Ph.D. thesis]. Toronto, Canada: Department of Electrical and Computer Engineering University of Toronto; 2005. p. 188.
9. C Maxfield. The Design Warrior’s Guide to FPGAs: Devices, Tools and Flows. Amsterdam: Elsevier; 2004.
10. LJ Goeders, M Wainberg, A Somerville, et al. VTR 7.0: Next generation architecture and CAD system for FPGAs. ACM Transactions on Reconfigurable Technology and Systems. 2014; 7(2):1–30.
11. T Kumar, B Pandey, SHA Musavi, et al. CTHS based energy efficient thermal aware image ALU design on FPGA. Wireless Personal Communications. 2015; 83(1): 671–696. 12. Xilinx. Vivado Design Suite Designing with IP Tutorial User Guide. April 5, 2017.
13. NCK Choy, SJE Wilton. Activity based power estimation and characterization of DSP and multiplier blocks in FPGAs. International Conference on Field Programmable Technology. Bangkok, Thailand. 2006, Dec. 13–15.
14. D Elleouet, N Julien, D Houzet, JG Cousin, E Martin. Power consumption characterization and modeling of embedded memories in XILINX VIRTEX 400E FPGA. Proceedings of the Euromicro Symposium on Digital System Design. Rennes, France. 2004, 31 Aug–3 Sep.
15. A Amira, S Chandrasekaran. Power modeling and efficient FPGA implementation of FHT for signal processing. IEEE Transactions on VLSI Systems. 2007; 15(3): 286–295.
16. D Elleouet, N Julien, D Houzet. A high level SoC power estimation based on IP modeling. 20th Proceedings of IEEE International Parallel & Distributed Processing Symposium. Rhodes, Greece. 2006, April 25–29.
17. S Chandrasekaran, A Amira. A new behavioural power modelling approach for FPGA based custom cores. NASA/ESA Conference on Adaptive Hardware and Systems. Edinburgh, UK. 2007, Aug. 5–8.
18. Hassan N Abdallah. A Complete Power Estimation Methodology for DSP Blocks in FPGAs.International Symposium on Quality Electronic Design. Santa Clara, USA. 2012, March 19–21.
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Research & Reviews: A Journal of Embedded System & Applications
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| Volume | 9 |
| Issue | 1 |
| Received | March 17, 2021 |
| Accepted | March 25, 2021 |
| Published | April 2, 2021 |
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