jovdtt Volume: 14, Issue: 03 Year: 2024


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Editor Overview

jovdtt maintains an Editorial Board of practicing researchers from around the world, to ensure manuscripts are handled by editors who are experts in the field of study.

Dr. Brajesh Kumar Kaushik

Dr. Brajesh Kumar Kaushik

Professor
Indian Institute of Technology, Roorkee, Uttarakhand, India
Editor in Chief
Journal of VLSI Design Tools and Technology
Email :

Institutional Profile Link : http://ece.iitr.ac.in/brajesh_kumar_kaushik

Publisher

STM Journals, An imprint of Consortium e-Learning Network Pvt. Ltd.

E-mail: [email protected]
Tel: (+91) 0120- 4781 200, (+91) 9218093691
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5

Regular Issue  Subscription Original Research Published on :- Sep 30, 2024

RTL-to-GDS Implementation of a High-Speed On-Chip 32:1 Serializer Using Open-Source Tools

By  

 

Meet B. Sangani1, Pallavi G. Darji,
Abstract : Exploring the RTL-to-GDS implementation of a high-speed on-chip 32:1 serializer, this study investigates the integration of open-source tools within read more

[This section belongs to Journal of VLSI Design Tools and Technology (jovdtt)]

 

 

1-10
Regular Issue  Subscription Original Research Published on :- Sep 30, 2024

Performance Analysis of Schmitt Trigger Circuit for Noise-Free Chips

By  

 

Hetav Desai, Zaid Gugarman, Pallavi Darji, Mitesh Limbachia,
Abstract : At lower nodes of complementary metal-oxide semiconductor (CMOS) technology, noise within a chip increase due to a drastic increment in interconnects read more

[This section belongs to Journal of VLSI Design Tools and Technology (jovdtt)]

 

 

11-20
Regular Issue  Subscription Original Research Published on :- Sep 30, 2024

Design and Implementation of Low Latency 16-bit Full Adder

By  

 

Sandeep N. Uttarkar, K. B. Ramesh,
Abstract : In the new age world, modern technology has vast applications in various fields of engineering, medicine, and others. Digital electronics processing read more

[This section belongs to Journal of VLSI Design Tools and Technology (jovdtt)]

 

 

21-31
Regular Issue  Subscription Original Research Published on :- Oct 24, 2024

Simulation of Adder Circuit Using Reversible Gates in Verilog HDL

By  

 

Pranav Rao, K. B. Ramesh,
Abstract : The emerging field of quantum computing uses quantum logic gates. The reversibility of logic gates is an important aspect of quantum logic gates used read more

[This section belongs to Journal of VLSI Design Tools and Technology (jovdtt)]

 

 

32-38
Regular Issue  Subscription Review Article Published on :- Nov 16, 2024

Thevenin Impedance Networks for Spice Simulation Using Analog Behavioural Modelling

By  

 

K. Bharath kumar,
Abstract : PSPICE/OrCAD software analog behavioral modeling (FREQ) option is used to obtain equivalent circuits for Thevenin equivalent resistance to be used for read more

[This section belongs to Journal of VLSI Design Tools and Technology (jovdtt)]

 

 

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