Design and Implementation of Low Noise Power Low and High Speed Three Stage Comparator Using 16nm Technology

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    Vannala Bhavya

  1. Student, Holy Mary Institute of Technology and Science, Hyderabad, India


To meet the demands of quicker operation and reduced noise levels, this study proposes a new CMOS Three-based comparator version. Efficiency may be significantly improved by comparing the suggested model to existing ones. This is so because the suggested comparator would improve the efficiency of the current amplifier design. The suggested model drives the input pairs of the regenerator and the amplified stage, making for a quicker comparator. The structure allowed for significant time savings. To reduce noise, the suggested solution integrates an NMOS pair into a PMOS structure. The ARM architecture’s positive feedback characteristic enables excellent comparison efficiency and low static power consumption with negligible leakage currents. There are a few limitations, nevertheless, that must be considered. Leakage current, which was previously mentioned as the latch’s primary source current, is what restricts the comparators’ speed. This leakage current originates from the pair in the input stage of the Strong ARM. The regeneration phase of the proposed model includes an additional signal to further increase the speed of the suggested circuit. The 16nm BSIM4 Model will be used to verify the proposed model’s precision. According to the supplied model, a three-stage circuit may reduce noise by a factor of a few orders of magnitude while increasing speed by 34% compared to a two-stage circuit. Mentor Graphics’ 16nm BSIM4 Technology was used to verify the suggested model

Keywords: CMOS, PMOS, NMOS, BSIM4 Model, Leakage current

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Subscription Original Research
Received November 3, 2023
Accepted December 11, 2023

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