Focus and Scope
About the Journal
Journal of Microcontroller Engineering and Applications [2455-197X(e)] is a peer-reviewed hybrid open-access journal launched in 2014 focused on the rapid publication of fundamental research papers on all areas of Microprocessor Engineering & Applications.
Focus and Scope
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Microprocessor & Microcontroller System: Cellular phones, Personal Area Networks, host controller, Bluetooth devices, biometrics, cryptography, encryption system, classifications, binary classification, Gabor wavelet, geometric features, support vector machine classifiers, encryption schemes, memory footprint, Sensors, Infrared thermometer, Air temperature, Soil temperature, Datalogging, Soil moisture, Data-acquisition system, Communication system, Meteorological data, Random number generator, Chaotic system, Analog circuit, Big data analysis, Evaporative cooling, Sessile Droplets, Infiltrometer, Instrumentation, Coding, Random processes, Error detection codes, Safety.
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Microelectronic Devices and Circuits: Subthreshold swing, Low band gap material, Heterodielectric, Lithium microbattery, 3D design, Materials selection, Thin-film, Review, energy storage applications, Inkjet printing, Printed electronics, Prepress, Print layout, Radiation effects microscopy, Single event upset, Radiation hardened ICs, Photopolymerization, Liquid encapsulant, Microelectronic packaging, Optical band gap, Thermal properties, Dielectric properties, Nanodielectric, Structural dynamics, High thermal conductivity, Excellent electrical insulation, High thermal stability, Shape memory, indium tin oxide (ITO), CCD camera, Laser probing method, ESPi, Shearography, Thermal testing.
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Digital Circuits and Digital Signal Processor: Machine vision, Real-time, Inspection, Fruit quality, Near infrared, Color space, Gas detection, Hot-plate sensors, Temperature modulation, Clustering validation, Digital signal processor, Phase Locked Loop (DPLL), Ultrasonic motor, Piezoelectric, Speed control, Direction of Arrival (DOA) estimation, parallel computing, Multilevel inverter, Sinusoidal pulse width modulation, Total harmonic distortion analysis, ground clutter, the direction of arrival, Doppler frequencies, radar signal processing, Evolvable hardware, nanoscale, genetic algorithm, Soft Error Rate (SER), Characterization, Microwave, Noise, Scalability, Enhancement/depletion-mode HEMT, Fluorine plasma treatment, Planar process, High-temperature digital integrated circuits.
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Programmable Logic designing: Energy systems, Industrial control, Monitoring, programmable logic controller (PLC), Logic model, Evaluability assessment, Pattern matching, Triangulation, Data analysis, Multimethod, Inkjet printing, Flexible electronics, Programmable array logic, Quantum-dot Cellular Automata (QCA), Decoder, Interfacing, Recursion, Cell count, Crossover, Industrial control systems, Firmware, Modification attacks, Reverse engineering, Phasor estimation, Genetic algorithms, Field Programmable Gate Array, Alternative Transients Program, Conveyors, Robotics, Sensors, Mechatronics, Parabolic Through Solar Collector, Process Heat, Motion System.
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Graphics Processing Units: Non-rigid registration, Free-form deformation, Normalized mutual information, Graphics processing unit, Molecular dynamics, Polymer systems, GPU computing, Heterogeneous computing, Profiling, Optimization, Debugging, Hardware, Future trends, Gravitation, Stellar dynamics, Methods: N-body simulation, Methods: numerical, Method of Characteristics, Pair distribution function, Two-point correlation function, GPU programming, CUDA, Lattice Boltzmann method, Parallel computing, Ant colony optimization, Multiple colonies, Parallel metaheuristics.
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Instruction Set Architecture: Stellar dynamics, Method: N-body simulations, Cosmology: large-scale structure of the universe, Galaxies: formation, processor architecture, superscalar processor, Instruction level parallelism, DDG-based quantification, Packet-processing engine, Application-specific processor, Benchmark profiling, Architectural guideline, Verification, embedded operating systems, Secure architecture, High-confidence computing, Operational semantics, architecture description language LISA, automotive electronic, macrocell, System on Chip, SoC, RTL processor design.
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SoC, SoPC, MPoC, and NoC Designing: 2-covered path problem, Variable radii, Power-aware routing, Fault tolerance, Wireless body area networks, advertising, films, packaging, posters, signs, interactive media, 3D animation artist, banknote designer, cartoonist, graphic designer, graphic artist, layout designer, Web sites, CDs, advertising designer processor, memory modules, I/O peripherals, and custom hardware accelerators, single FPGA (field-programmable gate array) device, integrated chip (IC), CPU (Central Processing Unit), RAM (Random Access Memory), storage, ports, IP core, programmable embedded systems.
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ASIC, FPGA: Electron multiplier (GEM), neutron detector, bandwidth, Low power, Clock gating, Power consumption, Computer Vision, Gray, Image Processing, Watermarking, Multimedia, Low power, Run-time reconfiguration (RTR), Fault injection, cryptographic applications, hardware accelerators, coprocessors, elliptic curves, Hardware implementation, Spiking neural network (SNN), Photovoltaic system, perturb and observe (P&O) algorithm, Photovoltaic module, Inferencing, Accelerators, configurability, utmost importance, propagation delay, lookup tables, communication latency, saturation throughput, Physical Unclonable Functions (PUFs), Field-Programmable Gate Array, Hardware security, PUF applications.
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Leveraging Software Tools for Optimal Performance: Parallel programming, Spatial interpolation, Multi-core, Pipelining, LiDAR, Mist Computing, Fog Computing, Secure Architecture, Smart Health, Big Data Analytics, Chromatographic simulation, ACD/Labs, Loratadine, Physico-chemical prediction, Software integration, Interoperability, Informatics, Habitat modeling, Oceanography, Zinc oxide, Shape-controlled synthesis, PDMS composite, Flexible nanogenerator, Supercapacitor, Internet of things, Strategic management, Knowledge-based theory, Dynamics capability theory, Deep learning, Design-build-test-learn, Genome-scale modeling, Metabolic burdens.
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Optimizing Microarchitecture through Parallelism: Embedded and general-purpose processors, Thread-level parallelism exploitation, Multicore architectures, Performance, Energy, Energy-delay product, Topology optimization, Elasticity, Multiscale, Finite element method, Machine learning, Optimization space exploration, Spark, Bayesian optimization, Process–structure-property, Substrate patterning, Morphology, Process design, Parallelism, Review, GPU, Hardware architecture for deep learning, Accelerator, Distributed training, Parameter server, All reduce, Pruning, Tiling, Phase-field, Multi-physics, HPC, Solver, PACE3D, Constraint networks, Compilers, Loop transformation, Data transformation.
Keywords
- Data input
- Storage
- Processing
- Output devices
- Memory
- Power supply
- Drive technology
- Information and communication technologies
- Lighting equipment
- Signal processor
- Designing (SoC, SoPC, MPoC NoC )
- Integrated Circuits (ASIC, FPGA)