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Design and Simulation of Forging Die Towards Improving Life of Closed Die

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u00a0Akshay S. Nandalgaonkar, Sachin C. Borse,

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nJanuary 9, 2023 at 6:43 am

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Forging is the metal forming process which is used for forming complex shaped component with geometrical accuracy. More than fifty percent of the forgings are processed through this way. Forged components required in many engineering sectors, most of them in the automotive sector. The majority of the safety critical component and load bearing structural components are process through it. By using forging process production of complex component is faster with less material waste. It is very difficult to do number of experimental testing and production trials are being done in the industry in order to develop a strongly formed manufacturing process of complex component. Such practices involve huge investment in tools and raw materials as well as valuable time and efforts. To take the virtual trials and simulation-based design finite element method is best suitable tool. At lower cost it would lead to improvement in life of die. As a sample case, a real-life automotive driveline component like yoke, is taken for investigation. Based on finite element analysis simulation is dine in Simufact. Different trials were done by using a forging press machine and validated against those predicted in Simufact software. The relation between them was found to be similar and satisfactory. A yoke is used in the propeller shaft of heavy vehicles is considered as a sample component. The research involves analyzing the initial effects of (1) workpiece temperature, (2) friction, (3) die temperature, and (4) Flash Thickness were examined. To obtained the results the forging process was design in PTC Creo 3.0, simulated in Simufact Software and experimental setup and examined using two-level full factorial design of experiments (Analyzed with Minitab and MS. Excel). The product reviewed was at the Varsha Forging Waluj, Aurangabad.

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Volume :u00a0u00a011 | Issue :u00a0u00a01 | Received :u00a0u00a0March 24, 2021 | Accepted :u00a0u00a0April 1, 2021 | Published :u00a0u00a0April 15, 2021n[if 424 equals=”Regular Issue”][This article belongs to Journal of VLSI Design Tools & Technology(jovdtt)] [/if 424][if 424 equals=”Special Issue”][This article belongs to Special Issue Design and Simulation of Forging Die Towards Improving Life of Closed Die under section in Journal of VLSI Design Tools & Technology(jovdtt)] [/if 424]
Keywords Die life improvement, Simufact, ANOVA, Taguchi, modeling

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1. Metalworking. Materials Park, OH: Bulk Forming, ASM International; 2005.
2. Sedighi M, Tokmechi S. A new approach to preform design in forging process of complex parts. J Mater Process Technol. 2008;197(1–3):314–24. doi: 10.1016/j.jmatprotec.2007.06.043.
3. Dieter GE, Bacon DJ. Mechanical metallurgy. New York: McGraw-Hill; 1986.
4. Mayur D. Improvement in hot forging process using die materials; 2014.
5. Altan T, Ngaile G, Shen G, editors. Cold and hot forging: fundamentals and applications. ASM international; 2004.
6. Tomov B, Radev R, Gagov V. Influence of flash design upon process parameters of hot die forging. J Mater Process Technol. 2004;157–158:620–3. doi: 10.1016/j.jmatprotec.2004.07.124.
7. Kim H, Sweeney K, Altan T. Application of computer aided simulation to investigate metal flow in selected forging operations. J Mater Process Technol. 1994;46(1–2):127–54. doi: 10.1016/0924–0136(94)90107–4.
8. Sedighi M, Tokmechi S. A new approach to preform design in forging process of complex parts. J Mater Process Technol. 2008;197(1–3):314–24. doi: 10.1016/j.jmatprotec.2007.06.043.
9. Tomov BI, Gagov VI, Radev RH. Numerical simulations of hot die forging processes using finite element method. J Mater Process Technol. 2004;153–154:352–8. doi: 10.1016/j.jmatprotec.2004.04.051.
10. Dieter GE, Kuhn HA, Semiatin SL, editors. Handbook of workability and process design. ASM international; 2003.
11. Krishnaiah K, Shahabudeen P. Applied design of experiments and Taguchi methods. PHI Learning Pvt. Ltd; 2012.
12. Phadke MS. Quality engineering using robust design. Prentice Hall PTR; 1995.

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[if 424 not_equal=”Regular Issue”] Regular Issue[/if 424] Open Access Article

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Journal of VLSI Design Tools & Technology

ISSN: 2249-474X

Editors Overview

jovdtt maintains an Editorial Board of practicing researchers from around the world, to ensure manuscripts are handled by editors who are experts in the field of study.

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    By  [foreach 286]n

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    Akshay S. Nandalgaonkar, Sachin C. Borse

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  1. Research Scholar, Assistant Professor,Deogiri Institute of Engineering and Management Studies, Deogiri Institute of Engineering and Management Studies,Aurangabad, Maharashtra, Aurangabad, Maharashtra,India, India

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Abstract

nForging is the metal forming process which is used for forming complex shaped component with geometrical accuracy. More than fifty percent of the forgings are processed through this way. Forged components required in many engineering sectors, most of them in the automotive sector. The majority of the safety critical component and load bearing structural components are process through it. By using forging process production of complex component is faster with less material waste. It is very difficult to do number of experimental testing and production trials are being done in the industry in order to develop a strongly formed manufacturing process of complex component. Such practices involve huge investment in tools and raw materials as well as valuable time and efforts. To take the virtual trials and simulation-based design finite element method is best suitable tool. At lower cost it would lead to improvement in life of die. As a sample case, a real-life automotive driveline component like yoke, is taken for investigation. Based on finite element analysis simulation is dine in Simufact. Different trials were done by using a forging press machine and validated against those predicted in Simufact software. The relation between them was found to be similar and satisfactory. A yoke is used in the propeller shaft of heavy vehicles is considered as a sample component. The research involves analyzing the initial effects of (1) workpiece temperature, (2) friction, (3) die temperature, and (4) Flash Thickness were examined. To obtained the results the forging process was design in PTC Creo 3.0, simulated in Simufact Software and experimental setup and examined using two-level full factorial design of experiments (Analyzed with Minitab and MS. Excel). The product reviewed was at the Varsha Forging Waluj, Aurangabad.n

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Keywords: Die life improvement, Simufact, ANOVA, Taguchi, modeling

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References

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1. Metalworking. Materials Park, OH: Bulk Forming, ASM International; 2005.
2. Sedighi M, Tokmechi S. A new approach to preform design in forging process of complex parts. J Mater Process Technol. 2008;197(1–3):314–24. doi: 10.1016/j.jmatprotec.2007.06.043.
3. Dieter GE, Bacon DJ. Mechanical metallurgy. New York: McGraw-Hill; 1986.
4. Mayur D. Improvement in hot forging process using die materials; 2014.
5. Altan T, Ngaile G, Shen G, editors. Cold and hot forging: fundamentals and applications. ASM international; 2004.
6. Tomov B, Radev R, Gagov V. Influence of flash design upon process parameters of hot die forging. J Mater Process Technol. 2004;157–158:620–3. doi: 10.1016/j.jmatprotec.2004.07.124.
7. Kim H, Sweeney K, Altan T. Application of computer aided simulation to investigate metal flow in selected forging operations. J Mater Process Technol. 1994;46(1–2):127–54. doi: 10.1016/0924–0136(94)90107–4.
8. Sedighi M, Tokmechi S. A new approach to preform design in forging process of complex parts. J Mater Process Technol. 2008;197(1–3):314–24. doi: 10.1016/j.jmatprotec.2007.06.043.
9. Tomov BI, Gagov VI, Radev RH. Numerical simulations of hot die forging processes using finite element method. J Mater Process Technol. 2004;153–154:352–8. doi: 10.1016/j.jmatprotec.2004.04.051.
10. Dieter GE, Kuhn HA, Semiatin SL, editors. Handbook of workability and process design. ASM international; 2003.
11. Krishnaiah K, Shahabudeen P. Applied design of experiments and Taguchi methods. PHI Learning Pvt. Ltd; 2012.
12. Phadke MS. Quality engineering using robust design. Prentice Hall PTR; 1995.

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Journal of VLSI Design Tools & Technology

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[if 344 not_equal=””]ISSN: 2249-474X[/if 344]

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Volume 11
Issue 1
Received March 24, 2021
Accepted April 1, 2021
Published April 15, 2021

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Design of Decoder Using Domino Logic Circuit for VLSI

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By [foreach 286]u00a0

u00a0K. Rama Krishna Reddy, Sai Teja Ankuru, Divya Pillutla, Varthya Shirisha,

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nJanuary 9, 2023 at 6:39 am

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Dissipation of power from a circuit is the major issue in the design of any VLSI circuit, which decreases the life span of a device/system. NMOS and PMOS circuits are very slow while switching the state from low to high. The speed of the circuit can be increased by decreasing resistance. This process in turn increases the static power dissipation. So, because of these disadvantages, CMOS circuits are used in many applications. For any CMOS circuit, the dissipation of power can be both static and dynamic. Dynamic dissipation in CMOS circuits occurs because of the switching of states. However, the static power dissipation is negligible in the circuit. Circuits designed using the domino model are used in various applications, like full adders, multiplexers, in memory as address selectors, comparators, and arithmetic circuits. There are different issues in domino logic circuits, namely power consumption, speed, and power delay product. A model is designed based on various approaches to solve these issues.

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Volume :u00a0u00a011 | Issue :u00a0u00a03 | Received :u00a0u00a0April 25, 2022 | Accepted :u00a0u00a0April 30, 2022 | Published :u00a0u00a0May 6, 2022n[if 424 equals=”Regular Issue”][This article belongs to Journal of VLSI Design Tools & Technology(jovdtt)] [/if 424][if 424 equals=”Special Issue”][This article belongs to Special Issue Design of Decoder Using Domino Logic Circuit for VLSI under section in Journal of VLSI Design Tools & Technology(jovdtt)] [/if 424]
Keywords Domino Logic Circuit, High speed, Low power

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1. Aishwarya, Jagadish Venkatraman Naik, Kshithija, Mahesh Biradar “Design of Low Power and High-Speed VLSI Domino Logic Circuit”. 2018 4th International Conference on Applied and Theoretical Computing and Communication Technology [ICATCCT]. 6-8 Sept. 2018; Mangalore, India. US: IEEE Press; 2020.
2. Rajneesh Sharma, Shekhar Verma, “Comparative Analysis of Static and Dynamic CMOS Logic Design”. 5th IEEE International Conference on Advanced Computing & Communication Technologies [ICACCT-2011]. https://www.apiit.edu.in/downloads/all%20chapters/CHAPTER- 49.pdf
3. Saurabh Sharma, Sanjeev Maheshwari, Sanjeev Kumar, Vrince Vimal, “Elimination of Charge Sharing Problem in Dynamic Circuit”, Journal of Engineering, Computers & Applied Sciences (JEC&AS). April 2013; 2(4): 15-19.
4. Rajesh Kumar Patjoshi, Ch. Suvarsha, S. K. Irfan Ali, S. K. Mastan Basha, D. Anjum. “Design and Analysis of Novel High-Performance CMOS Domino-Logic for High-Speed Applications”, ARPN Journal of Engineering and Applied Sciences. September 2017; 12(17): 5109-5114.
5. Muralidharan J. Manimegalai P. “A Literature Survey and Investigation of Various High- Performance Domino Logic Circuits”, ARPN Journal of Engineering and Applied Sciences. March 2016; 11(5): 3456- 3464.
6. MD Naushad Akhtar, Ashish Chouhan, Priya Kumari. “A Survey on Low Power High-Speed Domino Circuit in Low Power VLSI Design”. International Journal of Scientific Research & Engineering Trends. November- December 2019; 5(6): 1825-1830.
7. Volkan Kursun, Eby G. Friedman, “Domino Logic with Variable Threshold Voltage Keeper”. IEEE Transactions on Very Large-Scale Integration (VLSI) Systems. December 2003; 11(6): 1080-1093.
8. Ravi Mohan, Divyanshu Rao, Ankita Sharma, “Design and Implementation of Domino Logic Circuit in CMOS”, Journal of Network Communications and Emerging Technologies (JNCET). December 2016; 6(12): 14-17.
9. Ajay Kumar Dadoria, Uday Panwar. “”Comparison on Different Domino Logic Design for High- Performance and Leakage-Tolerant Wide OR Gate””. International Journal of Engineering Research and Applications. November-December 2013; 3(6): 2048-2052.
10. Nikhil Saxena, Sonal Sona. “”Leakage current reduction in CMOS circuits using stacking effect””. International Journal of Application or Innovation in Engineering & Management. November 2013; 2(11): 213-216.
11. Farshad Moradi, Tuan Vu Cao, Elenal, Vatajelu. “”Domino logic designs for high performance and leakage-tolerant applications””. Integration. June 2013; 46(3): 247-254.
12. Jyoti Shrivastava, Paresh Rawat. “”Comparative Analysis of Various Domino Logic Circuits for Improvement of Power and Delay Calculation””. International Journal of Computer Applications. (0975 – 8887) April 2017; 163(1): 30-34.
13. M. Hanumanthu, N. Bala Dastagiri, B. Abdul Rahim, P. Somasundar. “Design and Comparative Analysis of Domino Logic Styles” Indian Journal of Science and Technology. September 2016; 9(33): 1-6. DOI: 10.17485/ijst/2016/v9i33/99618.
14. Jyoti Shrivastava, Paresh Rawat, “A Novel Approach for Improvement of Power and Delay on Various Domino Logic Circuits”, International Journal of Engineering Trends and Technology (IJETT). March 2017; 45(9): 454-460.
15. Shilpa kamde, Jitesh Shinde, Sanjay Badjate, Pratik Hajare, “Comparative Analysis Domino Logic Based Techniques for VLSI Circuit”, International Journal of Computers & Technology.August 2013; 12(8): 3803-3808.

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[if 424 not_equal=”Regular Issue”] Regular Issue[/if 424] Open Access Article

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Journal of VLSI Design Tools & Technology

ISSN: 2249-474X

Editors Overview

jovdtt maintains an Editorial Board of practicing researchers from around the world, to ensure manuscripts are handled by editors who are experts in the field of study.

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  1. Assistant Professor, Student, Student, Student,Vasavi College of Engineering (Autonomous), Vasavi College of Engineering (Autonomous), Vasavi College of Engineering (Autonomous), Vasavi College of Engineering (Autonomous),Hyderabad, Telangana, Hyderabad, Telangana, Hyderabad, Telangana, Hyderabad, Telangana,India, India, India, India

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Abstract

nDissipation of power from a circuit is the major issue in the design of any VLSI circuit, which decreases the life span of a device/system. NMOS and PMOS circuits are very slow while switching the state from low to high. The speed of the circuit can be increased by decreasing resistance. This process in turn increases the static power dissipation. So, because of these disadvantages, CMOS circuits are used in many applications. For any CMOS circuit, the dissipation of power can be both static and dynamic. Dynamic dissipation in CMOS circuits occurs because of the switching of states. However, the static power dissipation is negligible in the circuit. Circuits designed using the domino model are used in various applications, like full adders, multiplexers, in memory as address selectors, comparators, and arithmetic circuits. There are different issues in domino logic circuits, namely power consumption, speed, and power delay product. A model is designed based on various approaches to solve these issues.n

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Keywords: Domino Logic Circuit, High speed, Low power

n[if 424 equals=”Regular Issue”][This article belongs to Journal of VLSI Design Tools & Technology(jovdtt)]

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References

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1. Aishwarya, Jagadish Venkatraman Naik, Kshithija, Mahesh Biradar “Design of Low Power and High-Speed VLSI Domino Logic Circuit”. 2018 4th International Conference on Applied and Theoretical Computing and Communication Technology [ICATCCT]. 6-8 Sept. 2018; Mangalore, India. US: IEEE Press; 2020.
2. Rajneesh Sharma, Shekhar Verma, “Comparative Analysis of Static and Dynamic CMOS Logic Design”. 5th IEEE International Conference on Advanced Computing & Communication Technologies [ICACCT-2011]. https://www.apiit.edu.in/downloads/all%20chapters/CHAPTER- 49.pdf
3. Saurabh Sharma, Sanjeev Maheshwari, Sanjeev Kumar, Vrince Vimal, “Elimination of Charge Sharing Problem in Dynamic Circuit”, Journal of Engineering, Computers & Applied Sciences (JEC&AS). April 2013; 2(4): 15-19.
4. Rajesh Kumar Patjoshi, Ch. Suvarsha, S. K. Irfan Ali, S. K. Mastan Basha, D. Anjum. “Design and Analysis of Novel High-Performance CMOS Domino-Logic for High-Speed Applications”, ARPN Journal of Engineering and Applied Sciences. September 2017; 12(17): 5109-5114.
5. Muralidharan J. Manimegalai P. “A Literature Survey and Investigation of Various High- Performance Domino Logic Circuits”, ARPN Journal of Engineering and Applied Sciences. March 2016; 11(5): 3456- 3464.
6. MD Naushad Akhtar, Ashish Chouhan, Priya Kumari. “A Survey on Low Power High-Speed Domino Circuit in Low Power VLSI Design”. International Journal of Scientific Research & Engineering Trends. November- December 2019; 5(6): 1825-1830.
7. Volkan Kursun, Eby G. Friedman, “Domino Logic with Variable Threshold Voltage Keeper”. IEEE Transactions on Very Large-Scale Integration (VLSI) Systems. December 2003; 11(6): 1080-1093.
8. Ravi Mohan, Divyanshu Rao, Ankita Sharma, “Design and Implementation of Domino Logic Circuit in CMOS”, Journal of Network Communications and Emerging Technologies (JNCET). December 2016; 6(12): 14-17.
9. Ajay Kumar Dadoria, Uday Panwar. “”Comparison on Different Domino Logic Design for High- Performance and Leakage-Tolerant Wide OR Gate””. International Journal of Engineering Research and Applications. November-December 2013; 3(6): 2048-2052.
10. Nikhil Saxena, Sonal Sona. “”Leakage current reduction in CMOS circuits using stacking effect””. International Journal of Application or Innovation in Engineering & Management. November 2013; 2(11): 213-216.
11. Farshad Moradi, Tuan Vu Cao, Elenal, Vatajelu. “”Domino logic designs for high performance and leakage-tolerant applications””. Integration. June 2013; 46(3): 247-254.
12. Jyoti Shrivastava, Paresh Rawat. “”Comparative Analysis of Various Domino Logic Circuits for Improvement of Power and Delay Calculation””. International Journal of Computer Applications. (0975 – 8887) April 2017; 163(1): 30-34.
13. M. Hanumanthu, N. Bala Dastagiri, B. Abdul Rahim, P. Somasundar. “Design and Comparative Analysis of Domino Logic Styles” Indian Journal of Science and Technology. September 2016; 9(33): 1-6. DOI: 10.17485/ijst/2016/v9i33/99618.
14. Jyoti Shrivastava, Paresh Rawat, “A Novel Approach for Improvement of Power and Delay on Various Domino Logic Circuits”, International Journal of Engineering Trends and Technology (IJETT). March 2017; 45(9): 454-460.
15. Shilpa kamde, Jitesh Shinde, Sanjay Badjate, Pratik Hajare, “Comparative Analysis Domino Logic Based Techniques for VLSI Circuit”, International Journal of Computers & Technology.August 2013; 12(8): 3803-3808.

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[if 344 not_equal=””]ISSN: 2249-474X[/if 344]

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Volume 11
Issue 3
Received April 25, 2022
Accepted April 30, 2022
Published May 6, 2022

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Comparative Analysis of CMOS CNFET and Memristor Based Full Adder Circuits and CMOS Memristor Based Multiplexer Circuits

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u00a0Rumaisa Uzma, M.A. Sayyad,

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nJanuary 9, 2023 at 6:19 am

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Continued developments in microelectronics technology have led to a myriad of new compute- intensive applications at the micro-edge, such as artificial intelligence and signal and image processing. Multiplication is a crucial arithmetic process in such applications. However, large logic complexities typically seen in traditional multipliers generate combinatorial blocks with long chains of cascaded carry addition. As such, energy efficiency has remained a primary design challenge for these applications, when powered by batteries or emerging energy harvesters. Hardware multipliers are an essential component of signal processes and related algorithms embedded within numerous multimedia and communication systems. In Arithmetic Logic Unit (ALU) one-bit full adder is one of the most repeatedly used digital circuit component which is most integral functional unit of all computational circuit. In this paper CMOS CNFET, Memristor based full adder and Multiplexer circuits are implemented at 45nm, 180nm and 32nm technology and performance parameters such as Power Delay Product (PDP), Propagation Delay and Power Consumption are compared using Cadence Virtuoso, HSPICE and LTSPICE simulator software.

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Volume :u00a0u00a012 | Issue :u00a0u00a02 | Received :u00a0u00a0July 7, 2022 | Accepted :u00a0u00a0July 15, 2022 | Published :u00a0u00a0July 29, 2022n[if 424 equals=”Regular Issue”][This article belongs to Journal of VLSI Design Tools & Technology(jovdtt)] [/if 424][if 424 equals=”Special Issue”][This article belongs to Special Issue Comparative Analysis of CMOS CNFET and Memristor Based Full Adder Circuits and CMOS Memristor Based Multiplexer Circuits under section in Journal of VLSI Design Tools & Technology(jovdtt)] [/if 424]
Keywords CMOS, CNFET, Memristor Full Adder, Multiplexer, PDP

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1. Chandran Venkatesan, Thabsera Sulthana M, Sumithra M.G, Suriya M” Analysis of 1- bit full adder using different techniques in Cadence 45nm Technology” 2019 5th International Conference on Advanced Computing & Communication Systems (ICACCS). 15-16 March 2019; Coimbatore, India. US: IEEE Press; 2019.
2. Zarin Tabassum, Meem Shahrin, Aniqa Ibnat, Tawfiq Amin. “Comparative Analysis and Simulation of Different CMOS Full Adders Using Cadence in 90 nm Technology” 2018 3rd International Conference for Convergence in Technology (I2CT). April 06-08, 2018; The Gateway Hotel, XION Complex, Wakad Road, Pune, India. US: IEEE Press; 2018.
3. Himanshu Thapliyal, Fazel Sharifi,S. Dinesh Kumar. “Energy-Efficient Design of Hybrid MTJ/CMOS and MTJ/Nanoelectronics Circuits” IEEE Transactions on Magnetics. July 2018; 54(7).
4. Partha Bhattacharyya, Bijoy Kundu, Sovan Ghosh, et, al. “Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit” IEEE Transactions on Very Large-Scale Integration(VLSI) Systems. October 2015; 23(10): 2001-2008.
5. Sepehr Tabrizchi, Atiyeh Panahi, Fazel Sharifi, et, al. “Method for designing ternary adder cells based on CNFETs”. IET Circuits, Devices & Systems. July 2017; 11(5): 465-470.
6. Kawsar Haghshenas, Mona Hashemi, Tooraj Nikoubin. “Fast and Energy Efficient CNFET Adders with CDM and Sensitivity Based Device-Circuit Co-Optimization,” IEEE Transactions on Nanotechnology. July 2018; 17(4): 783-794.
7. Xuan Hu, Michael J. Schultis, Matthew Kramer, et, al. “Overhead Requirements for Stateful Memristor Logic” IEEE Transactions on Circuits and Systems–I: Regular Papers. January 2019; 66(1): 263-273.
8. Gongzhi Liu, Lijing Zheng, GuangYi Wang, YiRan Shen and Yan Liang, “A Carry Lookahead Adder Based on Hybrid CMOS-Memristor Logic Circuit”. IEEE Access. 2019; 7 : 43691-43696.
9. Lauren Guckert, Earl E. Swartzlander. “MAD Gates – Memristor Logic Design Using Driver Circuitry” IEEE Transactions on Circuits and Systems II: Express Briefs. February 2017; 64(2): 171-175.
10. Shokat Ganjeheizadeh Rohani, Nima Taherinejad, David. “A Semiparallel Full-Adder in IMPLY Logic”. IEEE Transactions on Very Large-Scale Integration (VLSI) Systems. January 2020 28(1): 297-301.
11. Saeed Haghiri, Ali Nemati, Soheil Feizi, et, al. “A Memristor Based Binary Multiplier.” 2017 2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE). 30 April-03 May 2017; Windsor, ON, Canada. US: IEEE Press; 2017.
12. Arindam Banerjee, Sohini Pal, Swapan Bhattacharyya, Debesh Kumar Das. “Memristor Based Modulo Multiplier Design For (2𝑛 − 1) and 2𝑛 Radix.” 2017 Devices for Integrated Circuit(DevIC). 23-24 March 2017; Kalyani, India. US: IEEE Press; 2017.
13. Neha Jagan, Raksha S, Namitha S. U. “Design Of Memristor Based Multiplier.” May 2019; International Research Journal of Engineering and Technology. 06(05): 7737-7743.
14. H. Shaltoot, A. H. Madian. “Memristor-based Modified Recoded-multiplicand Systolic Serial-Parallel Multiplier”. 2013 1st International Conference on Communications, Signal Processing, and their Applications (ICCSPA). 12-14 February 2013; Sharjah, United Arab Emirates. US: IEEE Press; 2013.
15. Ahmad Karimi, Abdalhossein Rezai, “Novel design for Memristor-based n to 1 multiplexer using new IMPLY logic approach.” IET Circuits, Devices & Systems. 2019; 13(5): 647-655.
16. Shengqi Yu, Ahmed Soltan‡, Rishad Shafik, Thanasin Bunnam, Fei Xia, Domenico Balsamo, Alex Yakovlev,” Current-Mode Carry-Free Multiplier Design using a Memristor-Transistor Crossbar Architecture.”2020 Design, Automation & Test in Europe Conference & Exhibition. 09-13 March, 2020; Grenoble, France. US: IEEE Press; 2020.
17. Xiaoping Wang, Qian Wu, Qiao Chen, Zhigang Zeng. “A Novel Design for Memristor-Based Multiplexer via NOT-Material Implication.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. July 2018; 37(7): 1436-1444.
18. Lauren Guckert, Earl E. Swartzlander. “Optimized Memristor-Based Multipliers.” IEEE Transactions on Circuits and Systems I: Regular Papers. February 2017; 64(2): 373-385.
19. Neha Jagan, Raksha S, Namitha S U, et, al. “Design Of Memristor Based Multiplier.”. International Research Journal of Engineering and Technology. May 2019; 06(05): 7737- 7743.
20. M. Micheal Priyanka, T. Ravi. “An Efficient Prompt Multiplexers Using Memristor.” 2016 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET). 23-25 March 2016; Chennai, India. US: IEEE Press; 2016.
21. Lakshmi S., Meenu Raj C., Deepti Krishnadas. “Optimization of Hybrid CMOS Designs Using a New Energy Efficient 1 Bit Hybrid Full Adder”. 2018 3rd International Conference on Communication and Electronics Systems (ICCES). 15-16 October 2018; Coimbatore, India. US: IEEE Press; 2018.
22. Arpana Verma, Shyam Akashe” Low Power Application for Nano Scaled Memristor based 2: 1 Multiplexer.”2015 International Conference on Communication Networks (ICCN). 19-21 November 2015; Gwalior, India. US: IEEE Press; 2016.

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[if 424 not_equal=”Regular Issue”] Regular Issue[/if 424] Open Access Article

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Journal of VLSI Design Tools & Technology

ISSN: 2249-474X

Editors Overview

jovdtt maintains an Editorial Board of practicing researchers from around the world, to ensure manuscripts are handled by editors who are experts in the field of study.

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    Rumaisa Uzma, M.A. Sayyad

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  1. Student, Professor,SRES’s Sanjivani College of Engineering, SRES’s Sanjivani College of Engineering,Kopargaon, Maharashtra, Kopargaon, Maharashtra,India, India

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Abstract

nContinued developments in microelectronics technology have led to a myriad of new compute- intensive applications at the micro-edge, such as artificial intelligence and signal and image processing. Multiplication is a crucial arithmetic process in such applications. However, large logic complexities typically seen in traditional multipliers generate combinatorial blocks with long chains of cascaded carry addition. As such, energy efficiency has remained a primary design challenge for these applications, when powered by batteries or emerging energy harvesters. Hardware multipliers are an essential component of signal processes and related algorithms embedded within numerous multimedia and communication systems. In Arithmetic Logic Unit (ALU) one-bit full adder is one of the most repeatedly used digital circuit component which is most integral functional unit of all computational circuit. In this paper CMOS CNFET, Memristor based full adder and Multiplexer circuits are implemented at 45nm, 180nm and 32nm technology and performance parameters such as Power Delay Product (PDP), Propagation Delay and Power Consumption are compared using Cadence Virtuoso, HSPICE and LTSPICE simulator software.n

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Keywords: CMOS, CNFET, Memristor Full Adder, Multiplexer, PDP

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References

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1. Chandran Venkatesan, Thabsera Sulthana M, Sumithra M.G, Suriya M” Analysis of 1- bit full adder using different techniques in Cadence 45nm Technology” 2019 5th International Conference on Advanced Computing & Communication Systems (ICACCS). 15-16 March 2019; Coimbatore, India. US: IEEE Press; 2019.
2. Zarin Tabassum, Meem Shahrin, Aniqa Ibnat, Tawfiq Amin. “Comparative Analysis and Simulation of Different CMOS Full Adders Using Cadence in 90 nm Technology” 2018 3rd International Conference for Convergence in Technology (I2CT). April 06-08, 2018; The Gateway Hotel, XION Complex, Wakad Road, Pune, India. US: IEEE Press; 2018.
3. Himanshu Thapliyal, Fazel Sharifi,S. Dinesh Kumar. “Energy-Efficient Design of Hybrid MTJ/CMOS and MTJ/Nanoelectronics Circuits” IEEE Transactions on Magnetics. July 2018; 54(7).
4. Partha Bhattacharyya, Bijoy Kundu, Sovan Ghosh, et, al. “Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit” IEEE Transactions on Very Large-Scale Integration(VLSI) Systems. October 2015; 23(10): 2001-2008.
5. Sepehr Tabrizchi, Atiyeh Panahi, Fazel Sharifi, et, al. “Method for designing ternary adder cells based on CNFETs”. IET Circuits, Devices & Systems. July 2017; 11(5): 465-470.
6. Kawsar Haghshenas, Mona Hashemi, Tooraj Nikoubin. “Fast and Energy Efficient CNFET Adders with CDM and Sensitivity Based Device-Circuit Co-Optimization,” IEEE Transactions on Nanotechnology. July 2018; 17(4): 783-794.
7. Xuan Hu, Michael J. Schultis, Matthew Kramer, et, al. “Overhead Requirements for Stateful Memristor Logic” IEEE Transactions on Circuits and Systems–I: Regular Papers. January 2019; 66(1): 263-273.
8. Gongzhi Liu, Lijing Zheng, GuangYi Wang, YiRan Shen and Yan Liang, “A Carry Lookahead Adder Based on Hybrid CMOS-Memristor Logic Circuit”. IEEE Access. 2019; 7 : 43691-43696.
9. Lauren Guckert, Earl E. Swartzlander. “MAD Gates – Memristor Logic Design Using Driver Circuitry” IEEE Transactions on Circuits and Systems II: Express Briefs. February 2017; 64(2): 171-175.
10. Shokat Ganjeheizadeh Rohani, Nima Taherinejad, David. “A Semiparallel Full-Adder in IMPLY Logic”. IEEE Transactions on Very Large-Scale Integration (VLSI) Systems. January 2020 28(1): 297-301.
11. Saeed Haghiri, Ali Nemati, Soheil Feizi, et, al. “A Memristor Based Binary Multiplier.” 2017 2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE). 30 April-03 May 2017; Windsor, ON, Canada. US: IEEE Press; 2017.
12. Arindam Banerjee, Sohini Pal, Swapan Bhattacharyya, Debesh Kumar Das. “Memristor Based Modulo Multiplier Design For (2𝑛 − 1) and 2𝑛 Radix.” 2017 Devices for Integrated Circuit(DevIC). 23-24 March 2017; Kalyani, India. US: IEEE Press; 2017.
13. Neha Jagan, Raksha S, Namitha S. U. “Design Of Memristor Based Multiplier.” May 2019; International Research Journal of Engineering and Technology. 06(05): 7737-7743.
14. H. Shaltoot, A. H. Madian. “Memristor-based Modified Recoded-multiplicand Systolic Serial-Parallel Multiplier”. 2013 1st International Conference on Communications, Signal Processing, and their Applications (ICCSPA). 12-14 February 2013; Sharjah, United Arab Emirates. US: IEEE Press; 2013.
15. Ahmad Karimi, Abdalhossein Rezai, “Novel design for Memristor-based n to 1 multiplexer using new IMPLY logic approach.” IET Circuits, Devices & Systems. 2019; 13(5): 647-655.
16. Shengqi Yu, Ahmed Soltan‡, Rishad Shafik, Thanasin Bunnam, Fei Xia, Domenico Balsamo, Alex Yakovlev,” Current-Mode Carry-Free Multiplier Design using a Memristor-Transistor Crossbar Architecture.”2020 Design, Automation & Test in Europe Conference & Exhibition. 09-13 March, 2020; Grenoble, France. US: IEEE Press; 2020.
17. Xiaoping Wang, Qian Wu, Qiao Chen, Zhigang Zeng. “A Novel Design for Memristor-Based Multiplexer via NOT-Material Implication.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. July 2018; 37(7): 1436-1444.
18. Lauren Guckert, Earl E. Swartzlander. “Optimized Memristor-Based Multipliers.” IEEE Transactions on Circuits and Systems I: Regular Papers. February 2017; 64(2): 373-385.
19. Neha Jagan, Raksha S, Namitha S U, et, al. “Design Of Memristor Based Multiplier.”. International Research Journal of Engineering and Technology. May 2019; 06(05): 7737- 7743.
20. M. Micheal Priyanka, T. Ravi. “An Efficient Prompt Multiplexers Using Memristor.” 2016 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET). 23-25 March 2016; Chennai, India. US: IEEE Press; 2016.
21. Lakshmi S., Meenu Raj C., Deepti Krishnadas. “Optimization of Hybrid CMOS Designs Using a New Energy Efficient 1 Bit Hybrid Full Adder”. 2018 3rd International Conference on Communication and Electronics Systems (ICCES). 15-16 October 2018; Coimbatore, India. US: IEEE Press; 2018.
22. Arpana Verma, Shyam Akashe” Low Power Application for Nano Scaled Memristor based 2: 1 Multiplexer.”2015 International Conference on Communication Networks (ICCN). 19-21 November 2015; Gwalior, India. US: IEEE Press; 2016.

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Regular Issue Open Access Article

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Journal of VLSI Design Tools & Technology

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[if 344 not_equal=””]ISSN: 2249-474X[/if 344]

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Volume 12
Issue 2
Received July 7, 2022
Accepted July 15, 2022
Published July 29, 2022

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Views: 1,236

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