Design and Simulation of Full Adder-Based CMOS 4-2 Compressor using CMOS XOR-XNOR Logic

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This is an unedited manuscript accepted for publication and provided as an Article in Press for early access at the author’s request. The article will undergo copyediting, typesetting, and galley proof review before final publication. Please be aware that errors may be identified during production that could affect the content. All legal disclaimers of the journal apply.

Year : 2025 | Volume : 12 | 03 | Page :
    By

    Pallavi Singh,

  • Harsh Vikram Singh,

  1. Student, Department of Electronics Engineering, Kalma Nehru Institute of Technology, Sultanpur, Uttar Pradesh, India
  2. Professor, Department of Electronics Engineering, Kalma Nehru Institute of Technology, Sultanpur, Uttar Pradesh, India

Abstract

This study utilizes the recent development of CMOS transistors to construct an energy-efficient Full adder-based CMOS 4-2 compressor. The CMOS Exclusive-OR-Exclusive-NOR component and multiplexer used in the transmission logic of the novel CMOS compressor include eight transistors. The XOR-XNOR logic style is the most efficient and effective due to its speed and reduced power consumption. Utilizing an operational supply voltage of 0.7 V and 90nm CMOS technology, the Cadence Virtuoso Tool can ascertain three parameters: the Power-Delay Product (PDP) and the maximum output delay. The proposed CMOS 4-2 compressor’s performance was evaluated against existing designs using a 0.7V supply. Simulation results demonstrate significant improvements in speed, power consumption, and power-delay product. Compared to traditional 4-2 compressors, the new design offers enhanced efficiency and better overall performance. These enhancements make the proposed compressor more suitable for low-power, high-speed applications, highlighting its potential in modern digital systems. The results confirm its superiority over previous designs in key performance parameters under identical operating conditions.

Keywords: Area, CMOS, MIMO diverse full adder, leakage power, leakage current, cadence

How to cite this article:
Pallavi Singh, Harsh Vikram Singh. Design and Simulation of Full Adder-Based CMOS 4-2 Compressor using CMOS XOR-XNOR Logic. Recent Trends in Electronics Communication Systems. 2025; 12(03):-.
How to cite this URL:
Pallavi Singh, Harsh Vikram Singh. Design and Simulation of Full Adder-Based CMOS 4-2 Compressor using CMOS XOR-XNOR Logic. Recent Trends in Electronics Communication Systems. 2025; 12(03):-. Available from: https://journals.stmjournals.com/rtecs/article=2025/view=229525


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Ahead of Print Subscription Original Research
Volume 12
03
Received 05/07/2025
Accepted 12/08/2025
Published 24/10/2025
Publication Time 111 Days
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